公开(公告)号：US09508589B2

公开(公告)日：2016-11-29

申请号：US14283162

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang ,  Jeffrey Junhao Xu ,  Xiangdong Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

Abstract translation: 制造中间线（MOL）层和包括MOL层的器件的方法。 根据本公开的一个方面的方法包括将半导体衬底的半导体器件的端子上的活性触点沉积硬掩模。 这种方法还包括图案化硬掩模以选择性地暴露一些有源触点并选择性地绝缘一些有源触点。 该方法还包括在图案化的硬掩模和暴露的有源触点上沉积导电材料，以将暴露的有源触点彼此连接在半导体器件的有效区域上。

公开(公告)号：US09496181B2

公开(公告)日：2016-11-15

申请号：US14581244

申请日：2014-12-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7851

Abstract: A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate. The fin-based structure may also include an isolation layer disposed between the fins and on the surface of the semiconductor substrate. The fin-based structure may also include a recessed isolation liner on sidewalls of the doped portion of the fins. An unlined doped portion of the fins may extend from the recessed isolation liner to an active portion of the fins at a surface of the isolation layer. The isolation layer is disposed on the unlined doped portion of the fins.

Abstract translation: 鳍状结构可以包括半导体衬底的表面上的翅片。 每个翅片可以包括靠近半导体衬底的表面的掺杂部分。 鳍状结构还可以包括设置在散热片之间和半导体衬底的表面上的隔离层。 鳍状结构还可以包括在散热片的掺杂部分的侧壁上的凹陷的隔离衬垫。 翅片的无衬里的掺杂部分可以从凹陷的隔离衬垫延伸到隔离层的表面处的翅片的有源部分。 隔离层设置在翅片的无衬里的掺杂部分上。

公开(公告)号：US09478541B2

公开(公告)日：2016-10-25

申请号：US14480156

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap ,  Roawen Chen

IPC: G06F17/50 ,  H01L27/088 ,  G03F7/00 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/0886 ,  G03F7/00 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract translation: 根据本公开的一个方面的用于半节点缩放电路布局的方法包括裸片上的垂直设备。 该方法包括降低管芯上的垂直装置的翅片间距和栅极间距。 该方法还包括缩放波长以限定电路布局的至少一个缩小区域几何图案。

公开(公告)号：US09478490B2

公开(公告)日：2016-10-25

申请号：US14483110

申请日：2014-09-10

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang ,  Jeffrey Junhao Xu

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/00 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/823475 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract translation: 线路（MOL）层中间的器件电容器结构包括第一MOL互连层。 第一MOL互连层可以包括半导体衬底的有源表面上的一组虚拟栅极触点之间的有源触点。 器件电容器结构还包括第二MOL互连层。 第二MOL互连层可以直接在活动触点的暴露的一个上包括一组堆叠的触点。 第二MOL互连层还可以包括在一些有源触点上的蚀刻停止层的部分上的一组飞越触点。 飞越触点和堆叠的触点可以提供一组器件电容器的端子。

公开(公告)号：US20160276455A1

公开(公告)日：2016-09-22

申请号：US14661953

申请日：2015-03-18

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Stanley Seungchul Song

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/4958 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32133 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/53238 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66568 ,  H01L29/78

Abstract: A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-K) gate dielectric region. The conductive cap is disposed on a surface of the metal gate region and on a surface of the high-K gate dielectric region, and the interconnect is disposed on the conductive cap. The conductive cap includes a conductive material that electrically connects the gate region to the interconnect.

Abstract translation: 半导体器件包括栅极区，导电帽和互连。 栅极区域（例如，金属栅极晶体管）包括金属栅极区域和高介电常数（高K）栅极电介质区域。 导电盖设置在金属栅极区域的表面上和高K栅极电介质区域的表面上，并且互连设置在导电盖上。 导电盖包括将栅极区域与互连电连接的导电材料。

公开(公告)号：US20160247714A1

公开(公告)日：2016-08-25

申请号：US14627653

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/535 ,  G06F17/50 ,  H01L21/311

CPC classification number: H01L21/76802 ,  G03F1/14 ,  G03F7/203 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/7045 ,  G03F7/70466 ,  G06F17/5077 ,  H01L21/31116 ,  H01L23/535

Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.

Abstract translation: 公开了基于电子束（e-beam）的半导体器件特征。 在特定方面，一种方法包括执行第一光刻工艺以在半导体器件上制造第一组切割图案特征。 从特征到有效区域的第一组切割图案特征的每个特征的距离大于或等于阈值距离。 该方法还包括执行电子束（e-beam）工艺以在半导体器件上制造第二切割图案特征。 第二切割图案特征从第二切割图案特征到有效区域的第二距离小于或等于阈值距离。

公开(公告)号：US20160240539A1

公开(公告)日：2016-08-18

申请号：US14620480

申请日：2015-02-12

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3213 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11

Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

Abstract translation: 一种装置包括耦合到位单元的第一金属层。 该装置还包括第三金属层，其包括耦合到位单元的写入字线。 该装置还包括在第一金属层和第三金属层之间的第二金属层。 第二金属层包括耦合到位单元的两个读字线。

公开(公告)号：US20160240485A1

公开(公告)日：2016-08-18

申请号：US14622516

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Da Yang ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/02 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/535

Abstract: An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).

Abstract translation: 电子设备包括中间线（MOL）堆叠。 电子器件包括顶部局部互连层和通过第一介电层将顶部局部互连层耦合到半导体器件的栅极的接触。 电子设备还包括在接触件和第一介电层之间的一个或多个隔离壁，其中一个或多个隔离壁包括氮化铝（AlN）。

公开(公告)号：US09379014B1

公开(公告)日：2016-06-28

申请号：US14803063

申请日：2015-07-18

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Mosaddiq Saifuddin

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

CPC classification number: H01L27/1104

Abstract: A static random-access memory (SRAM) array includes a first metal layer and a second metal layer. The metal layer includes multiple first source lines spanning multiple columns of cells. The multiple first source lines include a first source line and a second source line. The second metal layer includes multiple second source lines spanning multiple rows of cells. The SRAM array further includes a set of vias coupled to the multiple first source lines and to the multiple second source lines. A first via of the set of vias is coupled to the first source line and multiple vias of the set of vias are coupled to the second source line. Two vias of the multiple vias that are closest to the first via are each substantially the same distance from the first via.

Abstract translation: 静态随机存取存储器（SRAM）阵列包括第一金属层和第二金属层。 金属层包括跨多个单元格的多个第一源线。 多个第一源极线包括第一源极线和第二源极线。 第二金属层包括跨越多行单元的多个第二源极线。 SRAM阵列还包括耦合到多个第一源极线和多个第二源极线的一组通孔。 通孔组的第一通孔耦合到第一源极线，并且该组通孔的多个通孔耦合到第二源极线。 最靠近第一通孔的多个通孔的两个通孔各自与第一通孔基本相同。

公开(公告)号：US09378803B2

公开(公告)日：2016-06-28

申请号：US13842263

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang

IPC: G06F17/50 ,  G11C11/4074 ,  G11C5/14 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

CPC classification number: G11C11/4074 ,  G06F17/5072 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

Abstract: A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating device, a voltage provided to the memory array based on the operating voltage.

Abstract translation: 一种方法包括测量与存储器阵列相关联的传感器的温度。 该方法还包括在电压调节装置处基于温度和基于与存储器阵列相关联的制造数据来计算工作电压。 该方法还包括在电压调节装置处基于工作电压调节提供给存储器阵列的电压。