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    SHARED GLOBAL READ AND WRITE WORD LINES
    2.
    发明申请
    SHARED GLOBAL READ AND WRITE WORD LINES 有权
    共享全球阅读和写字线

    公开(公告)号：US20160141021A1

    公开(公告)日：2016-05-19

    申请号：US14546980

    申请日：2014-11-18

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Ping Liu ,  Kern Rim ,  Choh Fei Yeap

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0688 ,  H01L27/1104

    Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

    Abstract translation: 一种装置包括包括第一行位单元和第二行位单元的位单元阵列。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第一全局读取字线。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第二全局读取字线。 该装置还包括全局写入字线，其被配置为选择性地耦合到第一行位单元和第二行位单元。 第一个全局读取字线，第二个全局读取字线和全局写入字线位于公共金属层中。

    METHOD AND APPARATUS FOR SELECTIVELY IMPROVING INTEGRATED DEVICE PERFORMANCE
    5.
    发明申请
    METHOD AND APPARATUS FOR SELECTIVELY IMPROVING INTEGRATED DEVICE PERFORMANCE 有权
    用于选择性地改进集成设备性能的方法和装置

    公开(公告)号：US20140131799A1

    公开(公告)日：2014-05-15

    申请号：US14156785

    申请日：2014-01-16

    Applicant: QUALCOMM Incorporated

    Inventor： Zhongze Wang ,  Choh fei Yeap ,  Ping Liu

    IPC: H01L27/088 ,  H01L29/78

    CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/7833 ,  Y02D70/00

    Abstract: An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom.

    Abstract translation: 提供了一种用于选择性地提高集成电路性能的装置。 在一个示例中，根据集成电路布局制造集成电路。 集成电路布局的关键部分确定集成电路的速度，其中临界部分的至少一部分包括光晕注入区域，轻掺杂漏极（LDD）注入区域和源极漏极延伸（SDE）中的至少一个 ）植入区域。 标记层包括关键部分的包括所述卤素注入区，轻掺杂漏极（LDD）注入区和源极漏极延伸（SDE）注入区）中的至少一个的部分，并且包括形成的至少一个晶体管 由此。

    Shared global read and write word lines
    7.
    发明授权
    Shared global read and write word lines 有权
    共享全局读写字线

    公开(公告)号：US09455026B2

    公开(公告)日：2016-09-27

    申请号：US14546980

    申请日：2014-11-18

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Ping Liu ,  Kern Rim ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/419 ,  G11C8/14 ,  H01L27/06 ,  G11C8/16

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0688 ,  H01L27/1104

    Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

    Abstract translation: 一种装置包括包括第一行位单元和第二行位单元的位单元阵列。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第一全局读取字线。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第二全局读取字线。 该装置还包括全局写入字线，其被配置为选择性地耦合到第一行位单元和第二行位单元。 第一个全局读取字线，第二个全局读取字线和全局写入字线位于公共金属层中。

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