公开(公告)号：US09825100B2

公开(公告)日：2017-11-21

申请号：US15011759

申请日：2016-02-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuki Sekino ,  Takashi Izumida ,  Nobutoshi Aoki

IPC: H01L27/24 ,  H01L23/532 ,  H01L45/00 ,  H01L23/528 ,  G11C5/06

CPC classification number: H01L27/249 ,  G11C5/063 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/78 ,  G11C2213/79 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of conducting layers, a semiconductor layer, a variable resistive element, and a first wiring. The plurality of conducting layers are laminated in a first direction at predetermined pitches. The conducting layers extend in a second direction. The second direction is along the surface of the substrate. The semiconductor layer extends in the first direction. The variable resistive element is disposed at an intersection point between the plurality of conducting layers and the semiconductor layer. The first wiring is opposed to an inside of the semiconductor layer via a gate insulating film. The first wiring extends in the first direction. The semiconductor layer at least includes a first part and a second part. The first part is upward of the conducting layer on a lowermost layer. The second part is downward of the first part. The first part has a first length in a third direction. The third direction is intersecting the first direction and the second direction, and is along the surface of the substrate. The second part has a second length in the third direction. The second length is shorter than the first length.

公开(公告)号：US09818798B2

公开(公告)日：2017-11-14

申请号：US15173104

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Naoki Takeguchi ,  Hiroaki Iuchi

IPC: H01L21/306 ,  H01L27/24 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/10 ,  H01L21/311 ,  H01L45/00 ,  H01L21/302 ,  H01L29/78

CPC classification number: H01L27/2454 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823487 ,  H01L27/101 ,  H01L27/249 ,  H01L45/065 ,  H01L45/085 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.

公开(公告)号：US20170317144A1

公开(公告)日：2017-11-02

申请号：US15650526

申请日：2017-07-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kenichi MUROOKA

IPC: H01L27/24 ,  G11C5/02 ,  H01L45/00 ,  H01L29/66 ,  H01L21/768 ,  G11C5/06 ,  G11C7/10 ,  G11C13/00

CPC classification number: H01L27/2481 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/78 ,  H01L21/768 ,  H01L27/2454 ,  H01L29/66666 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1608

Abstract: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

公开(公告)号：US20170301731A1

公开(公告)日：2017-10-19

申请号：US15643031

申请日：2017-07-06

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio MASUOKA ,  Hiroki NAKAMURA

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/128 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1658 ,  H01L45/1675

Abstract: A method for producing a memory device and semiconductor device includes forming pillar-shaped phase change layers and lower electrodes in two or more rows and two or more columns on a semiconductor substrate. A reset gate insulating film is formed that surrounds the pillar-shaped phase change layers and the lower electrodes, and a reset gate is formed that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns.

公开(公告)号：US09780147B2

公开(公告)日：2017-10-03

申请号：US15209164

申请日：2016-07-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi Kanno ,  Takayuki Tsukamoto ,  Takamasa Okawa ,  Atsushi Yoshida

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/249 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2213/71 ,  H01L27/2454 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.

公开(公告)号：US20170271405A1

公开(公告)日：2017-09-21

申请号：US15388376

申请日：2016-12-22

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shuichi TORIYAMA ,  Tomonori KUROSAWA

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/10 ,  H01L23/528

CPC classification number: H01L27/249 ,  H01L23/528 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L29/1033 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile semiconductor memory device according to one embodiment includes: a first wiring extending in a first direction as a longitudinal direction thereof; a second wiring extending in a second direction as a longitudinal direction thereof, the second direction intersecting with the first direction; a memory cell disposed at an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element; a select transistor having one end connected to the second wiring; and a third wiring connected to the other end of the select transistor. A semiconductor layer included in the select transistor has a first impurity concentration at the second end. An impurity concentration of the semiconductor layer decrease to a second impurity concentration from the first impurity concentration as approaching to the first end from the second end.

公开(公告)号：US20170256588A1

公开(公告)日：2017-09-07

申请号：US15074338

申请日：2016-03-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Natsuki FUKUDA ,  Mutsumi OKAJIMA ,  Atsushi OGA ,  Toshiharu TANAKA ,  Takeshi YAMAGUCHI ,  Takeshi TAKAGI ,  Masanori KOMURA

IPC: H01L27/24 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L27/2481 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/7926

Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.

公开(公告)号：US09754665B2

公开(公告)日：2017-09-05

申请号：US15228216

申请日：2016-08-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yangyin Chen ,  Christopher J. Petti ,  Kun Hou

IPC: G11C13/00 ,  H01L45/00 ,  H01L23/528 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/55 ,  G11C2213/71 ,  H01L23/528 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1675

Abstract: A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.

公开(公告)号：US09741768B1

公开(公告)日：2017-08-22

申请号：US15087980

申请日：2016-03-31

Applicant: SanDisk Technologies Inc.

Inventor： Ashot Melik-Martirosian ,  Juan Saenz

IPC: H01L27/11521 ,  H01L27/24 ,  H01L45/00 ,  H01L21/02

CPC classification number: H01L27/249 ,  H01L21/02491 ,  H01L27/11521 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a memory cell including a nonvolatile memory material at an intersection of the vertical bit line and the multi-layer word line. The multi-layer word line includes a first conductive material layer and a second conductive material layer disposed above the first conductive material layer. The memory cell includes a working cell area encompassed by an intersection of the first conductive material layer and the nonvolatile memory material.

公开(公告)号：US20170221559A1

公开(公告)日：2017-08-03

申请号：US15228216

申请日：2016-08-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yangyin Chen ,  Christopher J. Petti ,  Kun Hou

IPC: G11C13/00 ,  H01L23/528 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/55 ,  G11C2213/71 ,  H01L23/528 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1675

Abstract: A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.