公开(公告)号：US20170256588A1

公开(公告)日：2017-09-07

申请号：US15074338

申请日：2016-03-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Natsuki FUKUDA ,  Mutsumi OKAJIMA ,  Atsushi OGA ,  Toshiharu TANAKA ,  Takeshi YAMAGUCHI ,  Takeshi TAKAGI ,  Masanori KOMURA

IPC: H01L27/24 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L27/2481 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/7926

Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.

公开(公告)号：US20160351624A1

公开(公告)日：2016-12-01

申请号：US14850527

申请日：2015-09-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsushi OGA ,  Mutsumi OKAJIMA ,  Takeshi YAMAGUCHI ,  Hiroyuki ODE ,  Toshiharu TANAKA ,  Natsuki FUKUDA

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/08 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1683

Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

Abstract translation: 根据一个实施例，该半导体存储器件包括第一导电层，存储层和第二导电层。 第一导电层以垂直于衬底的第一方向以预定间距层压。 第一导电层在与基板平行的第二方向上延伸。 第二导电层沿第一方向延伸。 存储层围绕第二导电层的圆周。 第一导电层经由存储层与第二导电层的侧表面接触。 存储单元设置在第一导电层和第二导电层的交点处。

公开(公告)号：US20160351628A1

公开(公告)日：2016-12-01

申请号：US14970082

申请日：2015-12-15

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Mutsumi OKAJIMA ,  Atsushi OGA ,  Takeshi YAMAGUCHI ,  Hiroyuki ODE ,  Toshiharu TANAKA ,  Natsuki FUKUDA

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/11565 ,  H01L27/2427 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/16

Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

Abstract translation: 在该半导体存储器件中，第一导电层沿第一方向排列并且沿与第一方向交叉的第二方向延伸。 第一导电层通过层间绝缘膜沿第三方向排列。 第三方向与第一方向和第二方向相交。 层间绝缘膜设置在沿第三方向排列的第一导电层之间，并沿第一方向延伸。 第二导电层设置在沿第三方向排列并沿第一方向延伸的第一导电层之间。 第二导电层具有与第一方向交叉的近似圆形的横截面形状。 可变电阻层围绕第二导电层的周边区域，并且设置在第二导电层和第一导电层之间的位置。