公开(公告)号：US09780057B2

公开(公告)日：2017-10-03

申请号：US14503086

申请日：2014-09-30

申请人： STATS ChipPAC, Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31

CPC分类号： H01L24/17 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/09133 ,  H01L2224/09135 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17133 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

公开(公告)号：US09768138B2

公开(公告)日：2017-09-19

申请号：US14976927

申请日：2015-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Ming-Fa Chen ,  Rung-De Wang

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/16 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/11831 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/35 ,  Y10T428/12361 ,  Y10T428/12396 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

摘要： A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.

公开(公告)号：US20170213803A1

公开(公告)日：2017-07-27

申请号：US15423159

申请日：2017-02-02

申请人： X-Celeprint Limited

发明人： Christopher Bower

IPC分类号： H01L23/00 ,  H05K1/18 ,  H01L25/07 ,  H01L21/683 ,  H01L23/31 ,  H01L25/075

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6838 ,  H01L23/3157 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/95 ,  H01L24/97 ,  H01L25/04 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/13013 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29026 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/7698 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1205 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/15788 ,  H05K1/18 ,  H05K3/20 ,  Y10T29/49128 ,  Y10T156/1039 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00

摘要： An active substrate includes a plurality of active components distributed over a surface of a destination substrate, each active component including a component substrate different from the destination substrate, and each active component having a circuit and connection posts on a process side of the component substrate. The connection posts may have a height that is greater than a base width thereof, and may be in electrical contact with the circuit and destination substrate contacts. The connection posts may extend through the surface of the destination substrate contacts into the destination substrate connection pads to electrically connect the connection posts to the destination substrate contacts.

公开(公告)号：US20170207139A1

公开(公告)日：2017-07-20

申请号：US15478133

申请日：2017-04-03

申请人： Micron Technology, Inc.

发明人： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02163 ,  H01L2224/0391 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

摘要： An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US09691738B2

公开(公告)日：2017-06-27

申请号：US14833840

申请日：2015-08-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zheng-Yi Lim ,  Yi-Wen Wu ,  Tzong-Hann Yang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC分类号： H01L23/52 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16505 ,  H01L2224/32135 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/81085 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81232 ,  H01L2224/81355 ,  H01L2224/81359 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/06 ,  H01L2924/00

摘要： A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

公开(公告)号：US09666551B1

公开(公告)日：2017-05-30

申请号：US15236814

申请日：2016-08-15

申请人： Samsung Electronics Co., Ltd.

发明人： Sun-kyoung Seo ,  Seung-kwan Ryu ,  Cha-jea Jo ,  Tae-Je Cho

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00

CPC分类号： H01L24/14 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014

摘要： The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

公开(公告)号：US09607957B2

公开(公告)日：2017-03-28

申请号：US15236016

申请日：2016-08-12

申请人： ROHM CO., LTD.

发明人： Katsumi Sameshima

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/08 ,  H01L23/3171 ,  H01L23/525 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/32 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/0556 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13006 ,  H01L2224/1301 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/32501 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

公开(公告)号：US09607822B2

公开(公告)日：2017-03-28

申请号：US15264262

申请日：2016-09-13

申请人： Lam Research Corporation

发明人： Bryan L. Buckalew ,  Mark L. Rea

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01J37/32 ,  C25D5/48 ,  C25D5/02 ,  C25D5/34 ,  C25D7/12 ,  H01L21/027 ,  H01L21/67 ,  H01L21/768 ,  G03F7/42

CPC分类号： H01L21/02068 ,  C23C18/1605 ,  C23C18/1803 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/123 ,  G03F7/427 ,  H01J37/32357 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/0206 ,  H01L21/0273 ,  H01L21/6723 ,  H01L21/76862 ,  H01L21/76873 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/1181 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/014

摘要： Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.

公开(公告)号：US09589891B2

公开(公告)日：2017-03-07

申请号：US14946517

申请日：2015-11-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Jie Chen ,  Ying-Ju Chen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/525

CPC分类号： H01L24/02 ,  H01L21/76895 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/08145 ,  H01L2224/08221 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01047

摘要： Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.

摘要翻译： 公开了用于半导体器件的封装装置及其制造方法。 在一些实施例中，包装装置包括设置在衬底上的接触垫，以及设置在衬底上的钝化层和/或聚合物层和接触垫的一部分。 后钝化互连（PPI）线设置在钝化层上并且耦合到接触焊盘的暴露部分。 PPI垫设置在钝化层上。 过渡元件设置在钝化层上并且耦合在PPI线和PPI衬垫之间。 过渡元件包括宽度大于PPI线的线。

公开(公告)号：US20170011906A1

公开(公告)日：2017-01-12

申请号：US15264262

申请日：2016-09-13

申请人： Lam Research Corporation

发明人： Bryan L. Buckalew ,  Mark L. Rea

IPC分类号： H01L21/02 ,  C25D5/48 ,  C25D5/02 ,  G03F7/42 ,  C25D7/12 ,  H01L21/027 ,  H01L21/67 ,  H01L21/768 ,  H01J37/32 ,  C25D5/34

CPC分类号： H01L21/02068 ,  C23C18/1605 ,  C23C18/1803 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/123 ,  G03F7/427 ,  H01J37/32357 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/0206 ,  H01L21/0273 ,  H01L21/6723 ,  H01L21/76862 ,  H01L21/76873 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/1181 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/014

摘要： Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.

摘要翻译： 本文中的某些实施例涉及用于在远程等离子体环境中处理部分制造的半导体衬底的方法和装置。 这些方法可以在晶片级封装（WLP）工艺的上下文中进行。 所述方法可以包括将衬底暴露于还原等离子体以从底层种子层去除光致抗蚀剂浮渣和/或氧化。 在一些情况下，通过一系列等离子体处理除去光致抗蚀剂浮渣，包括暴露于含氧等离子体，然后暴露于还原等离子体。 在一些实施例中，进一步使用含氧等离子体在电镀之后从基板表面剥离光致抗蚀剂。 该等离子体条之后可以进行涉及暴露于还原等离子体的等离子体处理。 这里的等离子体处理可能涉及暴露于多工具电镀设备的等离子体处理模块内的远程等离子体。