公开(公告)号：US11640797B2

公开(公告)日：2023-05-02

申请号：US17215230

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Dong-Il Park

IPC: G09G3/30 ,  G09G3/3291 ,  G09G3/3233 ,  G09G3/29 ,  H03K19/0185

Abstract: A display driver integrated circuit (IC) is provided. The display driver IC includes a shift register configured to output a digital signal, and a digital-analog converter configured to receive the digital signal and generate a data voltage corresponding to the digital signal, wherein the digital-analog converter includes a delta-sigma modulator configured to output a modulated signal by receiving the digital signal and a first voltage, and performing delta-sigma modulation on the digital signal using the first voltage, and a level shifter configured to receive the modulated signal and a second voltage higher than the first voltage, and amplify the modulated signal using the second voltage.

公开(公告)号：US20230010252A1

公开(公告)日：2023-01-12

申请号：US17700825

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Wook Kim ,  Hongsik Kim ,  Heejun Kim ,  Seyoung Park ,  Seongjin Yoo ,  Minhong Yun ,  Daehan Han

IPC: G06F30/398 ,  G06F30/27

Abstract: Provided is a semiconductor process modeling system. The semiconductor process modeling system includes a preprocessing component configured to generate tensor data from raw data obtained from semiconductor manufacturing equipment, wherein, when the raw data is expressed as a raw matrix representing values of a plurality of process parameters for each of a plurality of wafers, at least one element of the raw matrix is omitted, when the tensor data is expressed as a tensor matrix representing values of a plurality of preprocessed process parameters for each of the plurality of wafers, the number of omitted elements of the tensor matrix is less than the number of omitted elements of the raw matrix, and the preprocessing component is configured to generate the tensor data by modifying the raw data based on at least one of characteristics of the semiconductor manufacturing equipment and characteristics of the plurality of process parameters.

公开(公告)号：US11322592B2

公开(公告)日：2022-05-03

申请号：US16881133

申请日：2020-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shigenobu Maeda ,  Seunghan Seo ,  Yeohyun Sung

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L29/22 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L29/51

Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.

公开(公告)号：US10411129B2

公开(公告)日：2019-09-10

申请号：US15877563

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

IPC: H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

公开(公告)号：US10403717B2

公开(公告)日：2019-09-03

申请号：US15686838

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Sun Lee ,  Chang-Woo Sohn ,  Chul-Sung Kim ,  Shigenobu Maeda ,  Young-Moon Choi ,  Hyo-Seok Choi ,  Sang-Jin Hyun

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/417

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

公开(公告)号：US09899386B2

公开(公告)日：2018-02-20

申请号：US15211012

申请日：2016-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Jeong Hwan Yang

IPC: H01L27/092 ,  H01L29/76 ,  H01L29/94 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/105 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

公开(公告)号：US09887202B2

公开(公告)日：2018-02-06

申请号：US15334411

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

IPC: H01L29/78 ,  H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L23/525 ,  H01L27/02

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

公开(公告)号：US09627390B2

公开(公告)日：2017-04-18

申请号：US14683151

申请日：2015-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon

IPC: H01L27/112 ,  G11C17/16 ,  H01L23/525

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.

公开(公告)号：US20160268416A1

公开(公告)日：2016-09-15

申请号：US15158859

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Bo-Ram Kim

IPC: H01L29/78 ,  H01L29/267 ,  H01L27/11 ,  H01L29/06 ,  H01L27/092 ,  H01L27/108

CPC classification number: H01L29/785 ,  H01L27/0924 ,  H01L27/108 ,  H01L27/11 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/66818

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the fin and the semiconductor layer include first and second semiconductor materials, respectively. Moreover, the method includes defining first and second active fins that include the second semiconductor material, by removing at least a portion of the fin. Related semiconductor devices are also provided.

公开(公告)号：US11695044B2

公开(公告)日：2023-07-04

申请号：US17352989

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shigenobu Maeda ,  Seunghan Seo ,  Yeohyun Sung

IPC: H01L29/16 ,  H01L29/165 ,  H01L29/267 ,  H01L29/778 ,  H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/22 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/1606 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/517

Abstract: A semiconductor device is provided and includes a substrate and a stack on the substrate. The stack includes plural active layers that are vertically stacked and spaced apart from each other, and plural gate electrodes that are on the active layers, respectively, and vertically stacked. Each active layer includes a channel layer under a corresponding one of the gate electrodes, and a source/drain layer disposed at a side of the channel layer and electrically connected to the channel layer. The channel layer is made of a two-dimensional atomic layer of a first material.