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公开(公告)号：US20170194481A1
公开(公告)日：2017-07-06
申请号：US15467100
申请日：2017-03-23
发明人： Hong He , Nicolas Loubet , Junli Wang
IPC分类号： H01L29/78 , H01L29/161 , H01L29/49 , H01L29/66
CPC分类号： H01L29/785 , H01L21/02236 , H01L21/02532 , H01L21/02592 , H01L21/2256 , H01L21/31116 , H01L29/1054 , H01L29/161 , H01L29/167 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/66818
摘要： A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.
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公开(公告)号：US20170018465A1
公开(公告)日：2017-01-19
申请号：US15220150
申请日：2016-07-26
发明人： Hong He , James Kuss , Nicolas Loubet , Junli Wang
IPC分类号： H01L21/84 , H01L27/092 , H01L21/02 , H01L29/161 , H01L21/306 , H01L21/324 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/845 , H01L21/0217 , H01L21/02532 , H01L21/30604 , H01L21/324 , H01L21/823821 , H01L21/823857 , H01L21/823864 , H01L21/823878 , H01L27/0924 , H01L27/1211 , H01L29/161
摘要： A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.
摘要翻译： 用于形成翅片的方法包括在体Si衬底的表面上生长SiGe层和硅层，从硅层和SiGe层图案化翅片结构，并用电介质填充物填充翅片结构。 形成沟槽以暴露翅片结构的端部。 翅片结构的第一个区域被阻挡。 通过从端部选择性地蚀刻翅片结构来去除第二区域的翅片结构的SiGe层，以形成填充有电介质材料的空隙。 翅片结构的硅层被暴露。 第一区域中的SiGe层被热氧化以将Ge驱动到硅层中，以在第一区域中的氧化物层上形成SiGe散热片，并在第二区域中在介电材料上形成硅散热片。
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公开(公告)号：US09502292B2
公开(公告)日：2016-11-22
申请号：US14856949
申请日：2015-09-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , STMicroelectronics, Inc. , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Bruce B. Doris , Shom Ponoth , Prasanna Khare , Qing Liu , Nicolas Loubet , Maud Vinet
IPC分类号： H01L21/336 , H01L21/76 , H01L21/20 , H01L21/425 , H01L21/768 , H01L21/762 , H01L29/06 , H01L29/786 , H01L21/02 , H01L29/08 , H01L29/417 , H01L29/66
CPC分类号： H01L21/76879 , H01L21/0217 , H01L21/76224 , H01L21/76283 , H01L21/76802 , H01L21/76877 , H01L21/76897 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/41783 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66628 , H01L29/78609
摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
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公开(公告)号：US20150255605A1
公开(公告)日：2015-09-10
申请号：US14201555
申请日：2014-03-07
发明人： Nicolas Loubet , Ali Khakifirooz , Pierre Morin , Sanjay C. Mehta
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.
摘要翻译： 描述了在全绝缘finFET中增加应变的方法和结构。 finFET结构可以形成在绝缘层上，并且包括绝缘的源极，沟道和漏极区域。 在制造期间，源区和漏区可以形成为悬挂结构。 应变诱导材料可以在四个相邻侧面上的源极和漏极区域周围形成，以便对finFET的沟道区域施加应力。
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公开(公告)号：US20140353767A1
公开(公告)日：2014-12-04
申请号：US13906505
申请日：2013-05-31
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/845 , H01L21/02529 , H01L21/02532 , H01L21/76224 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/6653 , H01L29/6656
摘要： On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.
摘要翻译： 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。
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26.发明授权Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods 有权具有具有第一和第二介电层的多个介电栅极堆叠的存储器件和相关方法公开(公告)号：US08860123B1
公开(公告)日：2014-10-14
申请号：US13852720
申请日：2013-03-28
发明人： Prasanna Khare , Stephane Allegret-Maret , Nicolas Loubet , Qing Liu , Hemanth Jagannathan , Lisa Edge , Kangguo Cheng , Bruce Doris
IPC分类号： H01L29/792 , H01L21/8238 , H01L29/423 , H01L29/66
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/11546 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
摘要翻译： 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。
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公开(公告)号：US11984493B2
公开(公告)日：2024-05-14
申请号：US17483216
申请日：2021-09-23
IPC分类号： H01L29/66 , H01L21/02 , H01L29/06 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66742 , H01L21/0259 , H01L29/0665 , H01L29/42392 , H01L29/78618 , H01L29/78696 , H01L29/66553
摘要： A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.
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公开(公告)号：US11935929B2
公开(公告)日：2024-03-19
申请号：US17507385
申请日：2021-10-21
IPC分类号： H01L29/417 , H01L21/8238 , H01L23/528 , H01L27/092 , H01L29/40 , H01L29/45
CPC分类号： H01L29/41725 , H01L21/823871 , H01L23/5286 , H01L27/0922 , H01L29/401 , H01L29/45
摘要： A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.
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公开(公告)号：US11894361B2
公开(公告)日：2024-02-06
申请号：US17545501
申请日：2021-12-08
发明人： Julien Frougier , Sagarika Mukesh , Anthony I. Chou , Andrew M. Greene , Ruilong Xie , Veeraraghavan S. Basker , Junli Wang , Effendi Leobandung , Jingyun Zhang , Nicolas Loubet
IPC分类号： H01L27/02 , H01L21/8234 , H01L21/84 , H01L27/12
CPC分类号： H01L27/0255 , H01L21/823481 , H01L21/84 , H01L27/0296 , H01L27/1207 , H01L27/1211
摘要： A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.
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公开(公告)号：US20230215768A1
公开(公告)日：2023-07-06
申请号：US17566402
申请日：2021-12-30
发明人： Ruilong Xie , Julien Frougier , Heng Wu , Nicolas Loubet
IPC分类号： H01L21/8238 , H01L29/423 , H01L29/06 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823821 , H01L29/0665 , H01L29/785 , H01L29/42392
摘要： An exemplary semiconductor apparatus includes a substrate that includes a first semiconductor. The substrate includes a main body and first and second island portions protruding upward from the main body. The apparatus also includes a bottom dielectric isolation layer that covers the substrate; a PFET with a plurality of gate-all-around (GAA) vertical channel fins above the first island portion and the bottom dielectric isolation layer; and an NFET with a plurality of gate-all-around (GAA) horizontal nanosheet layers above the second island portion and the bottom dielectric isolation layer.
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