公开(公告)号：US10283418B2

公开(公告)日：2019-05-07

申请号：US16027889

申请日：2018-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161

Abstract: A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

公开(公告)号：US10032912B2

公开(公告)日：2018-07-24

申请号：US14588221

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pierre Morin ,  Kangguo Cheng ,  Jody Fronheiser ,  Xiuyu Cai ,  Juntao Li ,  Shogo Mochizuki ,  Ruilong Xie ,  Hong He ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

公开(公告)号：US20170194481A1

公开(公告)日：2017-07-06

申请号：US15467100

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  Nicolas Loubet ,  Junli Wang

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2256 ,  H01L21/31116 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

公开(公告)号：US20170018465A1

公开(公告)日：2017-01-19

申请号：US15220150

申请日：2016-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L27/092 ,  H01L21/02 ,  H01L29/161 ,  H01L21/306 ,  H01L21/324 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161

Abstract: A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.

Abstract translation: 用于形成翅片的方法包括在体Si衬底的表面上生长SiGe层和硅层，从硅层和SiGe层图案化翅片结构，并用电介质填充物填充翅片结构。 形成沟槽以暴露翅片结构的端部。 翅片结构的第一个区域被阻挡。 通过从端部选择性地蚀刻翅片结构来去除第二区域的翅片结构的SiGe层，以形成填充有电介质材料的空隙。 翅片结构的硅层被暴露。 第一区域中的SiGe层被热氧化以将Ge驱动到硅层中，以在第一区域中的氧化物层上形成SiGe散热片，并在第二区域中在介电材料上形成硅散热片。

公开(公告)号：US20180323278A1

公开(公告)日：2018-11-08

申请号：US16020475

申请日：2018-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Bruce B. Doris ,  Hong He ,  Nicolas J. Loubet ,  Junli Wang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L27/092 ,  H01L29/165

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

公开(公告)号：US20180096883A1

公开(公告)日：2018-04-05

申请号：US15831761

申请日：2017-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Bruce Doris ,  Hong He ,  Qing Liu

IPC: H01L21/762 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L21/225

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

公开(公告)号：US09882006B2

公开(公告)日：2018-01-30

申请号：US15340624

申请日：2016-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  Nicolas Loubet ,  Junli Wang

IPC: H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L21/225 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2256 ,  H01L21/31116 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

公开(公告)号：US09461174B2

公开(公告)日：2016-10-04

申请号：US14449192

申请日：2014-08-01

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Hong He ,  James Kuss

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions. At least the side walls of the fin structures in the second region are covered with an epitaxially grown layer of second semiconductor material. A drive in process is performed to convert the fin structures in the second region from the first semiconductor material to the second semiconductor material. The first semiconductor material is, for example, silicon, and the second semiconductor material is, for example, silicon germanium or silicon carbide. The fin structures in the first region are provided for a FinFET of a first (for example, n-channel) conductivity type while the fin structures in the second region are provided for a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由第一半导体材料形成的衬底层包括相邻的第一和第二区域。 翅片结构由第一和第二区域中的基底层形成。 至少第二区域中的翅片结构的侧壁被外延生长的第二半导体材料层覆盖。 执行处理中的驱动以将第二区域中的鳍状结构从第一半导体材料转换成第二半导体材料。 第一半导体材料是例如硅，第二半导体材料是例如硅锗或碳化硅。 第一区域中的鳍结构被提供用于第一（例如，n沟道）导电类型的FinFET，而第二区域中的翅片结构被设置用于具有第二（例如，p沟道）导电性的FinFET 类型。

公开(公告)号：US20160218192A1

公开(公告)日：2016-07-28

申请号：US14607256

申请日：2015-01-28

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Bruce B. Doris ,  Hong He ,  Junli Wang ,  Nicolas J. Loubet

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

Abstract translation: 形成finFET晶体管器件的方法包括：在衬底上形成结晶的压缩应变硅锗（cSiGe）层; 掩蔽所述cSiGe层的第一区域以暴露所述cSiGe层的第二区域; 使cSiGe层的暴露的第二区域进行注入工艺，以使其底部非晶化，并将第二区域中的cSiGe层转变为弛豫的SiGe（rSiGe）层; 进行退火处理以使rSiGe层再结晶; 在rSiGe层上外延生长拉伸应变硅层; 以及在拉伸应变硅层和cSiGe层的第一区域中图案化翅片结构。

公开(公告)号：US20180315668A1

公开(公告)日：2018-11-01

申请号：US16027889

申请日：2018-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/324

CPC classification number: H01L21/845 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161

Abstract: A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.