公开(公告)号：US06462425B1

公开(公告)日：2002-10-08

申请号：US09429635

申请日：1999-10-29

Applicant: Toshihiro Iwasaki ,  Masatoshi Yasunaga ,  Satoshi Yamada ,  Kozo Harada ,  Michitaka Kimura

Inventor： Toshihiro Iwasaki ,  Masatoshi Yasunaga ,  Satoshi Yamada ,  Kozo Harada ,  Michitaka Kimura

IPC: H01L2940

CPC classification number: H01L21/563 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device allowing a mounting of a semiconductor substrate with narrow electrode pad interval on an insulated circuit board while securing a favorable insulation characteristic and a manufacturing method thereof are obtained. The semiconductor device includes an electrode pad formed on a semiconductor substrate; a connecting underlying metal film connected to the electrode pad; a connecting conductor establishing electrical conduction between the connecting underlying metal film and a terminal electrode on an insulated circuit board; and non-conductive resin surrounding the connecting conductor and filling a gap between the substrate and the insulated circuit board. Here, the connecting underlying metal film is not covered by the connecting conductor at least in a peripheral region including an outer peripheral portion thereof

Abstract translation: 获得能够在确保良好的绝缘特性的同时将具有窄电极焊盘间隔的半导体衬底安装在绝缘电路板上的半导体器件及其制造方法。 半导体器件包括形成在半导体衬底上的电极焊盘; 连接到电极焊盘的连接底层金属膜; 连接导体，其在连接的底层金属膜和绝缘电路板上的端子电极之间建立导电; 以及围绕连接导体的非导电树脂，并填充衬底和绝缘电路板之间的间隙。 这里，至少在包括其外周部分的周边区域中，连接基底金属膜不被连接导体覆盖

公开(公告)号：US5920770A

公开(公告)日：1999-07-06

申请号：US837960

申请日：1997-04-14

Applicant: Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

Inventor： Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

IPC: H01L21/60 ,  H01L21/56 ,  H01L21/68 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/32 ,  H01L23/485 ,  H01L25/10 ,  H05K3/30 ,  H05K3/34 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/568 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/10 ,  H01L25/105 ,  H05K3/303 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4813 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/2036 ,  H05K3/3442 ,  Y02P70/613

Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Abstract translation: 接合焊盘形成在半导体芯片的主表面上。 在半导体芯片的主表面上形成具有位于接合焊盘上的开口的绝缘层。 在接合焊盘上形成基底金属层。 在绝缘层上形成具有放置在基底金属层周围的部分的缓冲涂膜。 连接层形成在基底金属层上。 第一导体形成在连接层上。 形成仅露出第一导体的顶表面的密封树脂。 在第一导体的顶表面上形成笨重的第二导体。 因此，可以使树脂密封半导体封装紧凑并且具有改善的电特性和高可靠性。

公开(公告)号：US5296710A

公开(公告)日：1994-03-22

申请号：US868836

申请日：1992-04-15

Applicant: Katsuhiro Ohno ,  Akifumi Wada ,  Yousuke Sugiura ,  Masatoshi Yasunaga

Inventor： Katsuhiro Ohno ,  Akifumi Wada ,  Yousuke Sugiura ,  Masatoshi Yasunaga

IPC: G01J1/02 ,  G01J5/02 ,  G01J5/06 ,  G01J5/28 ,  G01J5/30 ,  H01L23/44 ,  H01L27/14 ,  H01L31/00 ,  H01L31/024 ,  G01J5/04

CPC classification number: G01J5/061 ,  H01L23/445 ,  H01L31/024 ,  H01L2224/48091 ,  H01L2924/12032 ,  H01L2924/19107

Abstract: An infrared radiation detector so adapted as to prevent the image signals from deteriorating due to the short length of leads extending within the cryogenic container with the infrared radiation sensing element accommodated within and to correspond to the increasing number of the leads and terminals, associated with a high density of elements. The infrared radiation detector is composed of an inner cylinder and an outer cylinder. The outer cylinder is disposed so as to lie in the same plane as the sub-package on which the multi-layered ceramic lead plate composed of a plurality of bonding pads for wire bonding, internally embedded lead layers, and plug-in terminals for fetching signals is mounted. The bonding pad of the sub-package is bonded to the bonding pad of the ceramic lead plate through a wire bonding.

Abstract translation: 一种红外辐射检测器，其适于防止图像信号由于在低温容器内延伸的引线的短长度而变差，其中红外辐射感测元件容纳在其内并且对应于越来越多的引线和端子，与 元素密度高。 红外线辐射检测器由内筒和外筒构成。 外筒设置成与其上由用于引线接合的多个接合焊盘，内部引入层和用于取出的插入式端子组成的多层陶瓷引线板的子封装体在同一平面中 信号被安装。 子封装的焊盘通过引线接合结合到陶瓷引线板的焊盘。

公开(公告)号：US5217910A

公开(公告)日：1993-06-08

申请号：US779498

申请日：1991-10-24

Applicant: Masahiro Shimizu ,  Katsuyoshi Mitsui ,  Yomiyuki Yama ,  Masatoshi Yasunaga

Inventor： Masahiro Shimizu ,  Katsuyoshi Mitsui ,  Yomiyuki Yama ,  Masatoshi Yasunaga

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/78

Abstract: First, a low-concentration impurity layer is formed by obliquely implanting an n-type impurity at a prescribed angle with respect to the surface of a p-type semiconductor substrate, using a gate electrode formed on the semiconductor substrate as a mask. Thereafter a sidewall spacer is formed on the sidewall of the gate electrode, and then a medium-concentration impurity layer is formed by obliquely implanting an n-type impurity to the surface of the semiconductor substrate. Thereafter a high-concentration impurity layer is formed by substantially perpendicularly implanting an n-type impurity with respect to the surface of the semiconductor substrate. According to this method, the low-concentration impurity layer in source and drain regions having triple diffusion structures can be accurately overlapped with the gate electrode, with no requirement for heat treatment for thermal diffusion.

Abstract translation: 首先，使用形成在半导体衬底上的栅电极作为掩模，通过以相对于p型半导体衬底的表面以规定角度倾斜注入n型杂质来形成低浓度杂质层。 此后，在栅电极的侧壁上形成侧壁间隔物，然后通过向半导体衬底的表面倾斜注入n型杂质形成中等浓度杂质层。 此后，通过相对于半导体衬底的表面基本垂直地注入n型杂质来形成高浓度杂质层。 根据该方法，具有三重扩散结构的源极和漏极区域中的低浓度杂质层可以与栅电极精确重叠，而不需要热扩散热处理。

公开(公告)号：US5018003A

公开(公告)日：1991-05-21

申请号：US571842

申请日：1990-08-21

Applicant: Masatoshi Yasunaga ,  Masanobu Kohara

Inventor： Masatoshi Yasunaga ,  Masanobu Kohara

IPC: H01L21/56 ,  H01L23/495

CPC classification number: H01L21/565 ,  H01L23/49503 ,  H01L24/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49121

Abstract: A lead frame includes a die pad for mounting thereon a semiconductor chip having a plurality of electrodes, a plurality of leads for electrical connection with the plurality of electrodes of the semiconductor chip, an outer frame disposed on the periphery of the die pad for supporting the die pad and the plurality of leads, and a resin guide portion extending to the vicinity of the die pad from the outer frame for guiding molten resin over and under the semiconductor chip during resin packaging. A semiconductor device manufacturing method includes mounting a semiconductor chip having electrodes on a substrate having a resin guiding portion for guiding a resin over and under the semiconductor chip during resin packaging; electrically connecting leads on the substrate to the electrodes; positioning the semiconductor chip and the substrate between a pair of mold halves injecting a molten resin into the mold to fill the cavity; and solidifying the resin.

Abstract translation: 引线框架包括用于安装其上具有多个电极的半导体芯片的芯片焊盘，用于与半导体芯片的多个电极电连接的多个引线，设置在芯片焊盘周边上的外框，用于支撑 芯片焊盘和多个引线，以及树脂引导部，其从外框延伸到芯片焊盘附近，用于在树脂封装期间将熔融树脂引导到半导体芯片的上方和下方。 一种半导体器件制造方法，包括在具有树脂引导部分的基板上安装具有电极的半导体芯片，用于在树脂封装期间将树脂引导到半导体芯片之上和之下; 将基板上的导线电连接到电极; 将半导体芯片和基板定位在将熔融树脂注入模具中以填充空腔的一对半模之间; 并固化树脂。

公开(公告)号：US20110074019A1

公开(公告)日：2011-03-31

申请号：US12889023

申请日：2010-09-23

Applicant: Masatoshi YASUNAGA ,  Hironori Matsushima ,  Kenya Hironaga ,  Soshi Kuroda

Inventor： Masatoshi YASUNAGA ,  Hironori Matsushima ,  Kenya Hironaga ,  Soshi Kuroda

IPC: H01L23/48

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/32145 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48844 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2924/20758 ,  H01L2924/2075 ,  H01L2924/00015

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract translation: 为了提高使用由铜制成的线进行引线接合的半导体器件的可靠性。 半导体器件被配置为使得铜线的端部（宽宽度部分）中的一个通过形成在半导体器件的半导体芯片的主表面（第一主表面）上的焊盘（电极焊盘）上的凸块接合 。 凸起由金制成，其是具有低于铜的硬度的金属材料，并且凸块的宽度比电线的宽幅部分的宽度窄。

公开(公告)号：US06469395B1

公开(公告)日：2002-10-22

申请号：US09567009

申请日：2000-05-09

Applicant: Tatsuto Nishihara ,  Masatoshi Yasunaga

Inventor： Tatsuto Nishihara ,  Masatoshi Yasunaga

IPC: H01L2348

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor device has a first semiconductor chip 2a, a wiring substrate 1 connected to the first semiconductor chip 2a, a first surrounding substrate 6a which has an opening at a position avoiding the first semiconductor chip 2a and which is connected onto the wiring substrate 1 by flip-chip bonding, and a second semiconductor chip 2b connected onto the first surrounding substrate 2a by flip-chip bonding. A second surrounding substrate 6b comprising a two or more number of substrate elements is used for the first surrounding substrate 6a.

Abstract translation: 半导体器件具有第一半导体芯片2a，连接到第一半导体芯片2a的布线基板1，第一周围基板6a，其在避开第一半导体芯片2a的位置处具有开口，并且通过以下方式连接到布线基板1上 倒装芯片接合以及通过倒装芯片接合连接到第一周围基板2a上的第二半导体芯片2b。 包括两个或多个基板元件的第二周围基板6b用于第一周围基板6a。

公开(公告)号：US5075240A

公开(公告)日：1991-12-24

申请号：US509850

申请日：1990-04-17

Applicant: Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

Inventor： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

IPC: H01L21/265 ,  H01L21/266

CPC classification number: H01L21/266 ,  Y10S438/972

Abstract: A conductive resist film is used as a mask in ion implantation. A portion of the conductive resist film is electrically connected to a semiconductor substrate. The charge of ions which enter the conductive resist film in ion implantation flows into the semiconductor substrate and dissipates therein.

Abstract translation: 在离子注入中使用导电抗蚀剂膜作为掩模。 导电抗蚀剂膜的一部分电连接到半导体衬底。 在离子注入中进入导电抗蚀剂膜的离子的电荷流入半导体衬底并在其中消散。