公开(公告)号：US20190139604A1

公开(公告)日：2019-05-09

申请号：US16220421

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Fu Lee ,  Yu-Der Chih ,  Hon-Jarn Lin

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of resistive random access memory (RRAM) devices respectively having a first electrode and a second electrode. A bit-line decoder is connected to the first electrode of the plurality of RRAM devices by a plurality of bit-lines. A current limiting element is connected to the second electrode of the plurality of RRAM devices by way of a plurality of access transistors. The current limiting element is configured to concurrently limit currents on the plurality of bit-lines.

公开(公告)号：US20180366192A1

公开(公告)日：2018-12-20

申请号：US15624413

申请日：2017-06-15

Applicant: Intel Corporation

Inventor： Richard G. Smolen ,  Rusli Kurniawan ,  Yue-Song He ,  Andy L. Lee ,  Jeffrey T. Watt ,  Christopher J. Pass

IPC: G11C13/00 ,  H03K19/00 ,  H03K19/177

CPC classification number: G11C13/0069 ,  G11C5/14 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C29/50008 ,  G11C2213/79 ,  H03K19/0002 ,  H03K19/1776

Abstract: Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.

公开(公告)号：US20180364931A1

公开(公告)日：2018-12-20

申请号：US16018837

申请日：2018-06-26

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau

IPC: G06F3/06 ,  G11C11/419 ,  G11C13/00 ,  G11C5/06 ,  G11C8/08

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/72

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

公开(公告)号：US20180358069A1

公开(公告)日：2018-12-13

申请号：US15870486

申请日：2018-01-12

Applicant: SanDisk Technologies LLC

Inventor： Supraja SUNDARESAN ,  Sung-en WANG ,  Khin HTOO ,  Primit MODI

IPC: G11C11/16 ,  G11C13/00 ,  G11C5/14

CPC classification number: G11C11/161 ,  G11C5/147 ,  G11C8/08 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/2253 ,  G11C11/2297 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/30 ,  G11C2213/71

Abstract: Disclosed is a device including a selected distributed driver, a first feedback control circuit, and a second feedback control circuit. The first feedback control circuit is coupled to the selected distributed driver. The first feedback control circuit is configured to maintain an output of the selected distributed driver within a first predetermined range. The second feedback control circuit is selectively coupled to the selected distributed driver and is configured to maintain the output of the selected distributed driver to be within a second predetermined range. The second predetermined range is within the first predetermined range.

公开(公告)号：US20180350823A1

公开(公告)日：2018-12-06

申请号：US15990611

申请日：2018-05-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L23/48

CPC classification number: H01L27/11286 ,  G11C5/025 ,  G11C13/0023 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C17/165 ,  G11C2213/71 ,  H01L23/481 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/24

Abstract: A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.

公开(公告)号：US20180350433A1

公开(公告)日：2018-12-06

申请号：US15570980

申请日：2015-09-25

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Miao Hu ,  Zhiyong Li ,  John Paul Strachan

IPC: G11C13/00 ,  G06G7/16

CPC classification number: G11C13/0007 ,  G06G7/16 ,  G11C5/05 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79

Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.

公开(公告)号：US10079058B1

公开(公告)日：2018-09-18

申请号：US15685788

申请日：2017-08-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Evangelos S. Eleftheriou ,  Manuel Le Gallo-Bourdeau ,  Abu Sebastian

IPC: G11C11/00 ,  G11C13/00 ,  G06N3/08 ,  G11C11/54 ,  G06G7/12 ,  G06N3/063

CPC classification number: G11C13/0021 ,  G06G7/12 ,  G06G7/16 ,  G06N3/063 ,  G06N3/088 ,  G11C11/54 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/77

Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising of row lines, of columns lines and of junctions arranged between the row lines and the column lines. Each junction comprises a programmable resistive memory element. The device comprises a signal generator and a readout circuit. The device is configured to perform a calibration procedure to compensate for conductance variations of the resistive memory elements. The calibration procedure is configured to program a calibration subset of the plurality of resistive memory elements to initial conductance values and to apply a constant calibration voltage to the row lines of the calibration subset. The device is configured to read calibration current values of the column lines of the calibration subset and to derive an estimation of a conductance variation parameter from the calibration current values.

公开(公告)号：US10074425B2

公开(公告)日：2018-09-11

申请号：US15632009

申请日：2017-06-23

Applicant: SONY CORPORATION

Inventor： Jun Sumino ,  Makoto Kitagawa

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0085 ,  G11C2213/79 ,  G11C2213/82

Abstract: Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory.

公开(公告)号：US20180240519A1

公开(公告)日：2018-08-23

申请号：US15797732

申请日：2017-10-30

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Manfre ,  Cesare Torti ,  Fabio Enrico Carlo Disegni

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C8/16 ,  G11C13/0004 ,  G11C13/0023

Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.

公开(公告)号：US10056142B2

公开(公告)日：2018-08-21

申请号：US15515317

申请日：2014-10-23

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning Ge ,  Jianhua Yang ,  Zhiyong Li ,  R. Stanley Williams

IPC: G11C15/00 ,  G11C13/00 ,  G11C7/10 ,  G11C15/04

CPC classification number: G11C13/004 ,  G11C7/1006 ,  G11C7/24 ,  G11C8/12 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0023 ,  G11C15/046

Abstract: A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set of logic indicators. Each first memristor is grouped with a corresponding second memristor during a memory read operation to generate a representative logic indicator.