公开(公告)号：US09558955B2

公开(公告)日：2017-01-31

申请号：US14795299

申请日：2015-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Shang Hsiao ,  Chi-Cherng Jeng ,  Chih-Mu Huang ,  Shin-Yeu Tsai ,  Fang-Wei Lin

IPC: H01L21/4763 ,  H01L21/3065 ,  H01L21/283 ,  H01L21/308 ,  H01L21/30 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/3065 ,  H01L21/02068 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/3003 ,  H01L21/3081 ,  H01L21/47635 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/82345 ,  H01L29/66545

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate stack over a semiconductor substrate. The method also includes performing a hydrogen-containing plasma treatment on the metal gate stack to modify a surface of the metal gate stack. The hydrogen-containing plasma treatment includes exciting a gas mixture including a first hydrogen-containing gas and a second hydrogen-containing gas to generate a hydrogen-containing plasma.

Abstract translation: 提供一种形成半导体器件结构的方法。 该方法包括在半导体衬底上形成金属栅叠层。 该方法还包括在金属栅极叠层上执行含氢等离子体处理以改变金属栅极叠层的表面。 含氢等离子体处理包括激发包括第一含氢气体和第二含氢气体的气体混合物以产生含氢等离子体。

公开(公告)号：US09281215B2

公开(公告)日：2016-03-08

申请号：US14080368

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Jeng ,  I-Chih Chen ,  Wen-Chang Kuo ,  Ying-Hao Chen ,  Ru-Shang Hsiao ,  Chih-Mu Huang

IPC: H01L27/085 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/32135 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/8238 ,  H01L27/085 ,  H01L27/088 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/6659

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括半导体衬底。 半导体器件还包括半导体衬底中的隔离结构并且围绕半导体衬底的有源区。 半导体器件包括半导体衬底上的栅极。 该栅极具有在有源区上方的中间部分和与该中间部分连接的两个端部。 每个端部具有长于中间部分的第二栅极长度的第一栅极长度并且位于隔离结构上方。

公开(公告)号：US20150263092A1

公开(公告)日：2015-09-17

申请号：US14205911

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Cing-Yao Chan ,  Chun-Ying Wang ,  Jen-Pan Wang

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/306 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L27/0928 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/7842

Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.

Abstract translation: 本公开涉及一种形成晶体管器件的方法，该晶体管器件具有沟道区域，该沟道区域包括具有提高器件性能的多个不同层的夹层膜堆叠以及相关联的器件。 在一些实施例中，通过选择性地蚀刻半导体衬底以沿着半导体衬底的顶表面形成凹槽来执行该方法。 在凹部内形成具有多个嵌套层的夹层膜叠层。 至少两个嵌套层包括改善晶体管器件性能的不同方面的不同材料。 在三明治薄膜叠层上形成栅极结构。 栅极结构控制具有夹层膜堆叠的沟道区域中的载流子的流动，其横向地位于设置在半导体衬底内的源极区域和漏极区域之间。

公开(公告)号：US11271111B2

公开(公告)日：2022-03-08

申请号：US16405057

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chun Kuan ,  I-Chih Chen ,  Chih-Mu Huang ,  Fu-Tsun Tsai ,  Sheng-Lin Hsieh ,  Kuan-Jung Chen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain feature in the substrate, protruding from the substrate, and on a sidewall surface of the gate structure. The semiconductor device structure also includes an insulating barrier structure in the substrate and partially covering the bottom and sidewalls of the source/drain feature.

公开(公告)号：US09812569B2

公开(公告)日：2017-11-07

申请号：US14224961

申请日：2014-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

公开(公告)号：US09466670B2

公开(公告)日：2016-10-11

申请号：US14205911

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Cing-Yao Chan ,  Chun-Ying Wang ,  Jen-Pan Wang

IPC: H02H9/00 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/7842

Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.

Abstract translation: 本公开涉及一种形成晶体管器件的方法，该晶体管器件具有沟道区域，该沟道区域包括具有提高器件性能的多个不同层的夹层膜堆叠以及相关联的器件。 在一些实施例中，通过选择性地蚀刻半导体衬底以沿着半导体衬底的顶表面形成凹槽来执行该方法。 在凹部内形成具有多个嵌套层的夹层膜叠层。 至少两个嵌套层包括改善晶体管器件性能的不同方面的不同材料。 在三明治薄膜叠层上形成栅极结构。 栅极结构控制具有夹层膜堆叠的沟道区域中的载流子的流动，其横向地位于设置在半导体衬底内的源极区域和漏极区域之间。

公开(公告)号：US20150243653A1

公开(公告)日：2015-08-27

申请号：US14189155

申请日：2014-02-25

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Chih-Fu Chang

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/76297 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate, an active region and a trench isolation. The active region is formed in the semiconductor substrate. The trench isolation is disposed adjacent to the active region. The trench isolation includes a lower portion and an upper portion. The upper portion is located on the lower portion. The upper portion has a width gradually decreased from a junction between the upper portion and the lower portion toward a top of the trench isolation. In a method for fabricating the semiconductor device, at first, the semiconductor substrate is etched to form a trench in the semiconductor substrate. Then, an insulator fills the trench to form the trench isolation. Thereafter, the gate structure is formed on the semiconductor substrate. Then, the semiconductor substrate is etched to form a recess adjacent to the trench isolation. Thereafter, at least one doped epitaxial layer grows in the recess.

Abstract translation: 半导体器件包括半导体衬底，有源区和沟槽隔离。 在半导体衬底中形成有源区。 沟槽隔离设置在有源区附近。 沟槽隔离包括下部和上部。 上部位于下部。 上部具有从上部和下部之间的接合部朝向沟槽隔离的顶部逐渐减小的宽度。 在制造半导体器件的方法中，首先蚀刻半导体衬底以在半导体衬底中形成沟槽。 然后，绝缘体填充沟槽以形成沟槽隔离。 此后，在半导体衬底上形成栅极结构。 然后，蚀刻半导体衬底以形成与沟槽隔离相邻的凹部。 此后，至少一个掺杂的外延层在凹槽中生长。

公开(公告)号：US12159921B2

公开(公告)日：2024-12-03

申请号：US17881317

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih Chen ,  Ru-Shang Hsiao ,  Ching-Pin Lin ,  Chih-Mu Huang ,  Fu-Tsun Tsai

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US20190229199A1

公开(公告)日：2019-07-25

申请号：US15877395

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Tsun Tsai ,  I-Chih Chen ,  Chih-Mu Huang ,  Jiun-Jie Huang ,  Jen-Pan Wang

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/3065

Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.

公开(公告)号：US10008501B2

公开(公告)日：2018-06-26

申请号：US15267328

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Cing-Yao Chan ,  Chun-Ying Wang ,  Jen-Pan Wang

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0928 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/7842

Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.