公开(公告)号：US11271111B2

公开(公告)日：2022-03-08

申请号：US16405057

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chun Kuan ,  I-Chih Chen ,  Chih-Mu Huang ,  Fu-Tsun Tsai ,  Sheng-Lin Hsieh ,  Kuan-Jung Chen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain feature in the substrate, protruding from the substrate, and on a sidewall surface of the gate structure. The semiconductor device structure also includes an insulating barrier structure in the substrate and partially covering the bottom and sidewalls of the source/drain feature.

公开(公告)号：US09812569B2

公开(公告)日：2017-11-07

申请号：US14224961

申请日：2014-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

公开(公告)号：US12159921B2

公开(公告)日：2024-12-03

申请号：US17881317

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih Chen ,  Ru-Shang Hsiao ,  Ching-Pin Lin ,  Chih-Mu Huang ,  Fu-Tsun Tsai

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US20190229199A1

公开(公告)日：2019-07-25

申请号：US15877395

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Tsun Tsai ,  I-Chih Chen ,  Chih-Mu Huang ,  Jiun-Jie Huang ,  Jen-Pan Wang

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/3065

Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.

公开(公告)号：US11600727B2

公开(公告)日：2023-03-07

申请号：US16892458

申请日：2020-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Chi Jeng ,  I-Chih Chen ,  Wen-Chang Kuo ,  Ying-Hao Chen ,  Ru-Shang Hsiao ,  Chih-Mu Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.

公开(公告)号：US11532728B2

公开(公告)日：2022-12-20

申请号：US16696261

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Tsun Tsai ,  Tong Jun Huang ,  I-Chih Chen ,  Chi-Cherng Jeng

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first fin extending from the substrate, a first gate structure over the substrate and engaging the first fin, and a first epitaxial feature partially embedded in the first fin and raised above a top surface of the first fin. The semiconductor device further includes a second fin extending from the substrate, a second gate structure over the substrate and engaging the second fin, and a second epitaxial feature partially embedded in the second fin and raised above a top surface of the second fin. A first depth of the first epitaxial feature embedded into the first fin is smaller than a second depth of the second epitaxial feature embedded into the second fin.

公开(公告)号：US10903336B2

公开(公告)日：2021-01-26

申请号：US16180623

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih Chen ,  Ru-Shang Hsiao ,  Ching-Pin Lin ,  Chih-Mu Huang ,  Fu-Tsun Tsai

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US20190139956A1

公开(公告)日：2019-05-09

申请号：US16151329

申请日：2018-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  I-Chih Chen ,  Chih-Mu Huang ,  Kai-Di Wu ,  Ming-Feng Lee ,  Ting-Chun Kuan

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.

公开(公告)号：US10153278B1

公开(公告)日：2018-12-11

申请号：US15717972

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Lin Hsieh ,  I-Chih Chen ,  Chih-Mu Huang ,  Ching-Pin Lin ,  Ru-Shang Hsiao ,  Ting-Chun Kuan

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/167 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack, spacers and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins comprise channel portions and flank portions beside the channel portions, the flank portions and the channel portions of the fins are protruded from the insulators, the flank portions of the fins and the channel portions of the fins have substantially a same height from top surfaces of the insulators, and each of the flank portions of the fins has a top surface and side surfaces adjoining the top surface. The at least one gate stack is disposed over the substrate, disposed on the insulators and over the channel portions of the fins. The spacers are disposed on the side surfaces of the flank portions of the fins. The epitaxy material portions are located above the top surfaces of the flank portions of the fins.

公开(公告)号：US10516048B2

公开(公告)日：2019-12-24

申请号：US15804887

申请日：2017-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.