公开(公告)号：US20150262929A1

公开(公告)日：2015-09-17

申请号：US14205878

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chih-Fu Chang ,  Jen-Pan Wang

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/7681 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates a method of forming a back-end-of-the-line (BEOL) metallization layer having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a metal interconnect layer within a sacrificial dielectric layer overlying a substrate. The sacrificial dielectric layer is removed to form a recess extending between first and second features of the metal interconnect layer. A protective liner is formed onto the sidewalls and bottom surface of the recess, and then a re-distributed ILD layer is deposited within the recess in a manner that forms an air gap at a position between the first and second features of the metal interconnect layer. The air gap reduces the dielectric constant between the first and second features of the metal interconnect layer.

Abstract translation: 本公开涉及一种形成后端行（BEOL）金属化层的方法，其具有设置在相邻金属互连特征之间的气隙，其提供具有低介电常数的级间介电材料，以及 相关联的装置。 在一些实施例中，通过在覆盖衬底的牺牲电介质层内形成金属互连层来执行该方法。 去除牺牲电介质层以形成在金属互连层的第一和第二特征之间延伸的凹部。 在凹槽的侧壁和底表面上形成保护衬垫，然后在凹槽内沉积再分布的ILD层，以在金属互连层的第一和第二特征之间的位置处形成气隙的方式 。 气隙减小金属互连层的第一和第二特征之间的介电常数。

公开(公告)号：US10062603B2

公开(公告)日：2018-08-28

申请号：US15223483

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chih-Fu Chang ,  Jen-Pan Wang

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/7681 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.

公开(公告)号：US09099439B2

公开(公告)日：2015-08-04

申请号：US14079950

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chih-Fu Chang ,  Jen-Pan Wang

IPC: H01L21/44 ,  H01L29/45 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/0262 ,  H01L21/28518 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76843 ,  H01L21/76855

Abstract: A semiconductor device includes a substrate, an epi-layer, an etch stop layer, an interlayer dielectric (ILD) layer, a silicide layer cap and a contact plug. The substrate has a first portion and a second portion neighboring to the first portion. The etch stop layer is disposed on the second portion. The ILD layer is disposed on the etch stop layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the ILD layer.

Abstract translation: 半导体器件包括衬底，外延层，蚀刻停止层，层间电介质（ILD）层，硅化物层帽和接触插塞。 衬底具有与第一部分相邻的第一部分和第二部分。 蚀刻停止层设置在第二部分上。 ILD层设置在蚀刻停止层上。 硅化物盖设置在外延层上。 接触插塞设置在硅化物盖上并被ILD层包围。

公开(公告)号：US20160336216A1

公开(公告)日：2016-11-17

申请号：US15223483

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chih-Fu Chang ,  Jen-Pan Wang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/7681 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.

Abstract translation: 本公开涉及具有设置在相邻金属互连特征之间的气隙的后端行（BEOL）金属化堆叠，其提供具有低介电常数的级间介电材料。 在一些实施例中，BEOL金属化堆叠具有设置在衬底上的级间介电层（ILD）层。 金属互连层设置在ILD层内，并且在金属互连层的第一特征和第二特征之间的位置处布置设置在ILD层内的气隙。 气隙具有上表面，第一曲线在布置在金属互连层的顶部下方的峰处满足第二曲线。 随着距离峰值的距离减小，第一曲线变得更陡峭，因为与峰值的距离减小，第二曲线变得更陡峭。

公开(公告)号：US09466670B2

公开(公告)日：2016-10-11

申请号：US14205911

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Cing-Yao Chan ,  Chun-Ying Wang ,  Jen-Pan Wang

IPC: H02H9/00 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/7842

Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.

Abstract translation: 本公开涉及一种形成晶体管器件的方法，该晶体管器件具有沟道区域，该沟道区域包括具有提高器件性能的多个不同层的夹层膜堆叠以及相关联的器件。 在一些实施例中，通过选择性地蚀刻半导体衬底以沿着半导体衬底的顶表面形成凹槽来执行该方法。 在凹部内形成具有多个嵌套层的夹层膜叠层。 至少两个嵌套层包括改善晶体管器件性能的不同方面的不同材料。 在三明治薄膜叠层上形成栅极结构。 栅极结构控制具有夹层膜堆叠的沟道区域中的载流子的流动，其横向地位于设置在半导体衬底内的源极区域和漏极区域之间。

公开(公告)号：US09449811B2

公开(公告)日：2016-09-20

申请号：US14205878

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Chih-Fu Chang ,  Jen-Pan Wang

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/7681 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates a method of forming a back-end-of-the-line (BEOL) metallization layer having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a metal interconnect layer within a sacrificial dielectric layer overlying a substrate. The sacrificial dielectric layer is removed to form a recess extending between first and second features of the metal interconnect layer. A protective liner is formed onto the sidewalls and bottom surface of the recess, and then a re-distributed ILD layer is deposited within the recess in a manner that forms an air gap at a position between the first and second features of the metal interconnect layer. The air gap reduces the dielectric constant between the first and second features of the metal interconnect layer.

Abstract translation: 本公开涉及一种形成后端行（BEOL）金属化层的方法，其具有设置在相邻金属互连特征之间的气隙，其提供具有低介电常数的级间介电材料，以及 相关联的装置。 在一些实施例中，通过在覆盖衬底的牺牲电介质层内形成金属互连层来执行该方法。 去除牺牲电介质层以形成在金属互连层的第一和第二特征之间延伸的凹部。 在凹槽的侧壁和底表面上形成保护衬垫，然后在凹槽内沉积再分布的ILD层，以在金属互连层的第一和第二特征之间的位置处形成气隙的方式 。 气隙减小金属互连层的第一和第二特征之间的介电常数。

公开(公告)号：US20190229199A1

公开(公告)日：2019-07-25

申请号：US15877395

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Tsun Tsai ,  I-Chih Chen ,  Chih-Mu Huang ,  Jiun-Jie Huang ,  Jen-Pan Wang

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/3065

Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.

公开(公告)号：US10256233B2

公开(公告)日：2019-04-09

申请号：US15883899

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Kuan Su ,  Yu-Hong Pan ,  Jen-Pan Wang ,  Tong-Min Weng ,  Tsung-Han Wu

IPC: H01L27/06 ,  H01L49/02

Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.

公开(公告)号：US20180342502A1

公开(公告)日：2018-11-29

申请号：US15883899

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Kuan Su ,  Yu-Hong Pan ,  Jen-Pan Wang ,  Tong-Min Weng ,  Tsung-Han Wu

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/60

Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.

公开(公告)号：US10008501B2

公开(公告)日：2018-06-26

申请号：US15267328

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Cing-Yao Chan ,  Chun-Ying Wang ,  Jen-Pan Wang

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0928 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/7842

Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.