公开(公告)号：US09577102B1

公开(公告)日：2017-02-21

申请号：US14865663

申请日：2015-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ting Hsiao ,  Cheng-Ta Wu ,  Lun-Kuang Tan ,  Liang-Yu Yen ,  Ting-Chun Wang ,  Tsung-Han Wu ,  Wei-Ming You

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/06

CPC classification number: H01L29/7856 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a gate includes: forming a dummy gate; forming an inter layer dielectric (ILD) laterally adjacent to the dummy gate; doping a dopant into the dummy gate and the ILD, in which a surface dopant concentration of the dummy gate is lower than a surface dopant concentration of the ILD; removing the dummy gate to form a cavity after doping the dopant into the dummy gate and the ILD; and forming the gate in the cavity.

Abstract translation: 一种形成栅极的方法包括：形成一个虚拟栅极; 形成横向邻近所述虚拟栅极的层间电介质（ILD）; 将掺杂剂掺杂到伪栅极和ILD中，其中伪栅极的表面掺杂剂浓度低于ILD的表面掺杂剂浓度; 在将掺杂剂掺杂到虚拟栅极和ILD中之后去除伪栅极以形成空腔; 并在腔中形成门。

公开(公告)号：US11610823B2

公开(公告)日：2023-03-21

申请号：US16673794

申请日：2019-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tong-Min Weng ,  Tsung-Han Wu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L21/3115 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

Abstract: A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

公开(公告)号：US10522349B2

公开(公告)日：2019-12-31

申请号：US16176533

申请日：2018-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Han Yang ,  Tsung-Han Wu ,  Chih-Wei Chang ,  Hsin-mei Lin ,  I-Chun Hsieh ,  Hsi-Yen Chang

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/306 ,  H01L21/266 ,  H01L21/265 ,  G03F7/38 ,  G03F7/20 ,  G03F7/26 ,  G03F7/09 ,  G03F7/16

Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.

公开(公告)号：US08954900B1

公开(公告)日：2015-02-10

申请号：US13955313

申请日：2013-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Ho ,  Kun-Ting Tsai ,  Tsung-Han Wu ,  Ke-Ying Su ,  Hsien-Hsin Sean Lee

IPC: G06F17/50

CPC classification number: G03F7/70466 ,  G03F7/70433

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Abstract translation: 集成电路的单层布局的一部分是多图案化的。 图案被划分为第一和第二组，通过第一掩模或第二掩模在单层上图案化。 对于每个图案的每个部分，在该部分和任一侧或两侧上的任何相邻图案之间确定间隔关系。 处理器计算将第一组分配给第一屏蔽，将第二组分配给第二屏蔽的第一电容（C），电阻（R）或电阻 - 电容（RC）成本，以及分配第一组的第二成本 基于间隔关系将第二掩模和第二组移动到第一掩模。 如果第一个成本低于第二个成本，则第一组被分配给第一个掩码，第二个组分配给第二个掩码。

公开(公告)号：US20190164745A1

公开(公告)日：2019-05-30

申请号：US16176533

申请日：2018-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Han Yang ,  Tsung-Han Wu ,  Chih-Wei Chang ,  Hsin-mei Lin ,  I-Chun Hsieh ,  Hsi-Yen Chang

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/306 ,  H01L21/266 ,  H01L21/265 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  G03F7/09 ,  G03F7/38

Abstract: A method includes depositing a target layer over a substrate; reducing a reflection of a light incident upon the target layer by implanting ions into the target layer, resulting in an ion-implanted target layer; coating a photoresist layer over the ion-implanted target layer; exposing the photoresist layer to the light using a photolithography process, wherein the target layer reduces reflection of the light at an interface between the ion-implanted target layer and the photoresist layer during the photolithography process; developing the photoresist layer to form a resist pattern; etching the ion-implanted target layer with the resist pattern as an etch mask; processing the substrate using at least the etched ion-implanted target layer as a process mask; and removing the etched ion-implanted target layer.

公开(公告)号：US10256233B2

公开(公告)日：2019-04-09

申请号：US15883899

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Kuan Su ,  Yu-Hong Pan ,  Jen-Pan Wang ,  Tong-Min Weng ,  Tsung-Han Wu

IPC: H01L27/06 ,  H01L49/02

Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.

公开(公告)号：US20180342502A1

公开(公告)日：2018-11-29

申请号：US15883899

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Kuan Su ,  Yu-Hong Pan ,  Jen-Pan Wang ,  Tong-Min Weng ,  Tsung-Han Wu

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/60

Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.

公开(公告)号：US20230207395A1

公开(公告)日：2023-06-29

申请号：US18113516

申请日：2023-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tong-Min WENG ,  Tsung-Han Wu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L21/3115 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/28123 ,  H01L21/02131 ,  H01L21/0217 ,  H01L29/4983 ,  H01L21/31155 ,  H01L21/823821 ,  H01L29/66545 ,  H01L27/0924 ,  H01L21/022 ,  H01L21/02126 ,  H01L21/02321 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/6656

Abstract: A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

公开(公告)号：US11158505B2

公开(公告)日：2021-10-26

申请号：US16721355

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Han Yang ,  Tsung-Han Wu ,  Chih-Wei Chang ,  Hsin-mei Lin ,  I-Chun Hsieh ,  Hsi-Yen Chang

IPC: H01L21/027 ,  H01L21/265 ,  H01L21/308 ,  H01L21/306 ,  H01L21/266 ,  G03F7/38 ,  G03F7/20 ,  G03F7/26 ,  G03F7/09 ,  G03F7/16 ,  H01L21/033

Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.

公开(公告)号：US10651296B2

公开(公告)日：2020-05-12

申请号：US16048904

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Han Wu ,  Tong-Min Weng ,  Chun-Yi Huang ,  Po-Ching Lee ,  Chih-Hsuan Hsieh ,  Shu-Ching Tsai

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/324 ,  H01L21/265

Abstract: Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.