知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.019 seconds)

    Shallow trench isolation structure
    1.
    发明授权
    Shallow trench isolation structure 有权
    浅沟隔离结构

    公开(公告)号：US09318371B2

    公开(公告)日：2016-04-19

    申请号：US14189155

    申请日：2014-02-25

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Chih-Fu Chang

    IPC: H01L23/34 ,  H01L21/76 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

    CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/76297 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    Abstract: A semiconductor device includes a semiconductor substrate, an active region and a trench isolation. The active region is formed in the semiconductor substrate. The trench isolation is disposed adjacent to the active region. The trench isolation includes a lower portion and an upper portion. The upper portion is located on the lower portion. The upper portion has a width gradually decreased from a junction between the upper portion and the lower portion toward a top of the trench isolation. In a method for fabricating the semiconductor device, at first, the semiconductor substrate is etched to form a trench in the semiconductor substrate. Then, an insulator fills the trench to form the trench isolation. Thereafter, the gate structure is formed on the semiconductor substrate. Then, the semiconductor substrate is etched to form a recess adjacent to the trench isolation. Thereafter, at least one doped epitaxial layer grows in the recess.

    Abstract translation: 半导体器件包括半导体衬底，有源区和沟槽隔离。 在半导体衬底中形成有源区。 沟槽隔离设置在有源区附近。 沟槽隔离包括下部和上部。 上部位于下部。 上部具有从上部和下部之间的接合部朝向沟槽隔离的顶部逐渐减小的宽度。 在制造半导体器件的方法中，首先蚀刻半导体衬底以在半导体衬底中形成沟槽。 然后，绝缘体填充沟槽以形成沟槽隔离。 此后，在半导体衬底上形成栅极结构。 然后，蚀刻半导体衬底以形成与沟槽隔离相邻的凹部。 此后，至少一个掺杂的外延层在凹槽中生长。

    AIR-GAP SCHEME FOR BEOL PROCESS
    3.
    发明申请
    AIR-GAP SCHEME FOR BEOL PROCESS 审中-公开
    用于BEOL过程的AIR-GAP方案

    公开(公告)号：US20160336216A1

    公开(公告)日：2016-11-17

    申请号：US15223483

    申请日：2016-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ru-Shang Hsiao ,  Chih-Fu Chang ,  Jen-Pan Wang

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

    CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/7681 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.

    Abstract translation: 本公开涉及具有设置在相邻金属互连特征之间的气隙的后端行（BEOL）金属化堆叠，其提供具有低介电常数的级间介电材料。 在一些实施例中，BEOL金属化堆叠具有设置在衬底上的级间介电层（ILD）层。 金属互连层设置在ILD层内，并且在金属互连层的第一特征和第二特征之间的位置处布置设置在ILD层内的气隙。 气隙具有上表面，第一曲线在布置在金属互连层的顶部下方的峰处满足第二曲线。 随着距离峰值的距离减小，第一曲线变得更陡峭，因为与峰值的距离减小，第二曲线变得更陡峭。

    Air-gap scheme for BEOL process
    4.
    发明授权
    Air-gap scheme for BEOL process 有权
    BEOL工艺气隙方案

    公开(公告)号：US09449811B2

    公开(公告)日：2016-09-20

    申请号：US14205878

    申请日：2014-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ru-Shang Hsiao ,  Chih-Fu Chang ,  Jen-Pan Wang

    IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/7681 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates a method of forming a back-end-of-the-line (BEOL) metallization layer having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a metal interconnect layer within a sacrificial dielectric layer overlying a substrate. The sacrificial dielectric layer is removed to form a recess extending between first and second features of the metal interconnect layer. A protective liner is formed onto the sidewalls and bottom surface of the recess, and then a re-distributed ILD layer is deposited within the recess in a manner that forms an air gap at a position between the first and second features of the metal interconnect layer. The air gap reduces the dielectric constant between the first and second features of the metal interconnect layer.

    Abstract translation: 本公开涉及一种形成后端行（BEOL）金属化层的方法，其具有设置在相邻金属互连特征之间的气隙，其提供具有低介电常数的级间介电材料，以及 相关联的装置。 在一些实施例中，通过在覆盖衬底的牺牲电介质层内形成金属互连层来执行该方法。 去除牺牲电介质层以形成在金属互连层的第一和第二特征之间延伸的凹部。 在凹槽的侧壁和底表面上形成保护衬垫，然后在凹槽内沉积再分布的ILD层，以在金属互连层的第一和第二特征之间的位置处形成气隙的方式 。 气隙减小金属互连层的第一和第二特征之间的介电常数。

    N/P MOS FinFET performance enhancement by specific orientation surface
    5.
    发明授权
    N/P MOS FinFET performance enhancement by specific orientation surface 有权
    N / P MOS FinFET通过特定方向表面增强性能

    公开(公告)号：US09209304B2

    公开(公告)日：2015-12-08

    申请号：US14179585

    申请日：2014-02-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ru-Shang Hsiao ,  Hung Pin Chen ,  Wei-Barn Chen ,  Chih-Fu Chang ,  Chih-Kang Chao ,  Ling-Sung Wang

    IPC: H01L29/78

    CPC classification number: H01L29/7853 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78642

    Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

    Abstract translation: 如本文将更详细地理解的，本公开提供FinFET技术，由此与常规FinFET相比，FinFET沟道区相对于半导体器件的晶格具有特定取向以提供增强的迁移率。 特别地，本公开为FinFET提供其晶格包括布置在（551）晶格平面上的硅原子的沟道区。 在这种配置中，沟道区的侧壁在原子水平上特别平滑，这倾向于促进比以前可实现的更高的载流子迁移率和更高的器件性能。

    Shallow Trench Isolation Structure
    6.
    发明申请
    Shallow Trench Isolation Structure 有权
    浅沟槽隔离结构

    公开(公告)号：US20150243653A1

    公开(公告)日：2015-08-27

    申请号：US14189155

    申请日：2014-02-25

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Chih-Fu Chang

    IPC: H01L27/088 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02

    CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/76297 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    Abstract: A semiconductor device includes a semiconductor substrate, an active region and a trench isolation. The active region is formed in the semiconductor substrate. The trench isolation is disposed adjacent to the active region. The trench isolation includes a lower portion and an upper portion. The upper portion is located on the lower portion. The upper portion has a width gradually decreased from a junction between the upper portion and the lower portion toward a top of the trench isolation. In a method for fabricating the semiconductor device, at first, the semiconductor substrate is etched to form a trench in the semiconductor substrate. Then, an insulator fills the trench to form the trench isolation. Thereafter, the gate structure is formed on the semiconductor substrate. Then, the semiconductor substrate is etched to form a recess adjacent to the trench isolation. Thereafter, at least one doped epitaxial layer grows in the recess.

    Abstract translation: 半导体器件包括半导体衬底，有源区和沟槽隔离。 在半导体衬底中形成有源区。 沟槽隔离设置在有源区附近。 沟槽隔离包括下部和上部。 上部位于下部。 上部具有从上部和下部之间的接合部朝向沟槽隔离的顶部逐渐减小的宽度。 在制造半导体器件的方法中，首先蚀刻半导体衬底以在半导体衬底中形成沟槽。 然后，绝缘体填充沟槽以形成沟槽隔离。 此后，在半导体衬底上形成栅极结构。 然后，蚀刻半导体衬底以形成与沟槽隔离相邻的凹部。 此后，至少一个掺杂的外延层在凹槽中生长。

    N/P MOS FINFET PERFORMANCE ENHANCEMENT BY SPECIFIC ORIENTATION SURFACE
    8.
    发明申请
    N/P MOS FINFET PERFORMANCE ENHANCEMENT BY SPECIFIC ORIENTATION SURFACE 有权
    N / P MOS FinFET性能通过特定方位表面增强

    公开(公告)号：US20150228794A1

    公开(公告)日：2015-08-13

    申请号：US14179585

    申请日：2014-02-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ru-Shang Hsiao ,  Hung Pin Chen ,  Wei-Barn Chen ,  Chih-Fu Chang ,  Chih-Kang Chao ,  Ling-Sung Wang

    IPC: H01L29/78

    CPC classification number: H01L29/7853 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78642

    Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

    Abstract translation: 如本文将更详细地理解的，本公开提供FinFET技术，由此与常规FinFET相比，FinFET沟道区相对于半导体器件的晶格具有特定取向以提供增强的迁移率。 特别地，本公开为FinFET提供其晶格包括布置在（551）晶格平面上的硅原子的沟道区。 在这种配置中，沟道区的侧壁在原子水平上特别平滑，这倾向于促进比以前可实现的更高的载流子迁移率和更高的器件性能。

    AIR-GAP SCHEME FOR BEOL PROCESS
    10.
    发明申请
    AIR-GAP SCHEME FOR BEOL PROCESS 有权
    用于BEOL过程的AIR-GAP方案

    公开(公告)号：US20150262929A1

    公开(公告)日：2015-09-17

    申请号：US14205878

    申请日：2014-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ru-Shang Hsiao ,  Chih-Fu Chang ,  Jen-Pan Wang

    IPC: H01L23/528 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/7681 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates a method of forming a back-end-of-the-line (BEOL) metallization layer having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a metal interconnect layer within a sacrificial dielectric layer overlying a substrate. The sacrificial dielectric layer is removed to form a recess extending between first and second features of the metal interconnect layer. A protective liner is formed onto the sidewalls and bottom surface of the recess, and then a re-distributed ILD layer is deposited within the recess in a manner that forms an air gap at a position between the first and second features of the metal interconnect layer. The air gap reduces the dielectric constant between the first and second features of the metal interconnect layer.

    Abstract translation: 本公开涉及一种形成后端行（BEOL）金属化层的方法，其具有设置在相邻金属互连特征之间的气隙，其提供具有低介电常数的级间介电材料，以及 相关联的装置。 在一些实施例中，通过在覆盖衬底的牺牲电介质层内形成金属互连层来执行该方法。 去除牺牲电介质层以形成在金属互连层的第一和第二特征之间延伸的凹部。 在凹槽的侧壁和底表面上形成保护衬垫，然后在凹槽内沉积再分布的ILD层，以在金属互连层的第一和第二特征之间的位置处形成气隙的方式 。 气隙减小金属互连层的第一和第二特征之间的介电常数。

Patent Agency Ranking