公开(公告)号：US20220165861A1

公开(公告)日：2022-05-26

申请号：US17669859

申请日：2022-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hoon LEE ,  Wan Don KIM ,  Jong Ho PARK ,  Sang Jin HYUN

IPC: H01L29/51 ,  H01L29/786 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

公开(公告)号：US20200350429A1

公开(公告)日：2020-11-05

申请号：US16932076

申请日：2020-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Soo KIM ,  Dong Hyun ROH ,  Koung Min RYU ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

公开(公告)号：US20190109135A1

公开(公告)日：2019-04-11

申请号：US16203946

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20180130905A1

公开(公告)日：2018-05-10

申请号：US15620631

申请日：2017-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun CHUNG ,  Jong Ho PARK ,  Seung Ha OH ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L21/324 ,  H01L21/283

CPC classification number: H01L29/7831 ,  B82Y10/00 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78696

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

公开(公告)号：US20170256544A1

公开(公告)日：2017-09-07

申请号：US15351673

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Suk CHAI ,  Hu Yong LEE ,  Sang Yong KIM ,  Taek Soo JEON ,  Won Keun CHUNG ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/306 ,  H01L21/311 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including a MOS transistor is provided. The semiconductor device may include a first MOS transistor including first source/drain regions, a first semiconductor layer between the first source/drain regions, a first gate electrode structure, and a first gate dielectric structure; and a second MOS transistor including second source/drain regions, a second semiconductor layer between the second source/drain regions, a second gate electrode structure, and a second gate dielectric structure. The first gate dielectric structure and the second gate dielectric structure include a first common dielectric structure; the first gate dielectric structure includes a first upper dielectric on the first common dielectric structure; the second gate dielectric structure includes the first upper dielectric and a second upper dielectric; and one of the first upper dielectric and the second upper dielectric is a material forming a dipole layer.

公开(公告)号：US20210257250A1

公开(公告)日：2021-08-19

申请号：US17308128

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Chae Ho NA ,  Gyu Hwan AHN ,  Dong Hyun ROH ,  Sang Jin HYUN

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.

公开(公告)号：US20210013207A1

公开(公告)日：2021-01-14

申请号：US17038964

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20190355825A1

公开(公告)日：2019-11-21

申请号：US16214537

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hyuk YIM ,  Kug Hwan KIM ,  Wan Don KIM ,  Jung Min PARK ,  Jong Ho PARK ,  Byoung Hoon LEE ,  Yong Ho HA ,  Sang Jin HYUN ,  Hye Ri HONG

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.

公开(公告)号：US20190295909A1

公开(公告)日：2019-09-26

申请号：US16441591

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baek KI ,  Tark-Hyun KO ,  Kun-Dae YEOM ,  Yong-Kwan LEE ,  Keun-Ho JANG ,  Sang Jin HYUN

IPC: H01L23/10 ,  H01L23/13 ,  H01L23/538 ,  H01L23/057 ,  H01L21/56

Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

公开(公告)号：US20180090495A1

公开(公告)日：2018-03-29

申请号：US15473031

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Sun LEE ,  Joon Gon LEE ,  Na Rae KIM ,  Chul Sung KIM ,  Do Hyun LEE ,  Ryuji TOMITA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7856

Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.