公开(公告)号：US20200168471A1

公开(公告)日：2020-05-28

申请号：US16439211

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOO HEE JANG ,  Seok Ho Kim ,  Hoon Joo NA ,  Kwang Jin Moon ,  Jae Hyung Park ,  Kyu Ha Lee

IPC: H01L21/321 ,  H01L27/146

Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region

公开(公告)号：US20180350983A1

公开(公告)日：2018-12-06

申请号：US16100804

申请日：2018-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun CHUNG ,  Jong Ho PARK ,  Seung Ha OH ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/324 ,  H01L29/06 ,  H01L21/283

CPC classification number: H01L29/7831 ,  B82Y10/00 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78696

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

公开(公告)号：US20190109135A1

公开(公告)日：2019-04-11

申请号：US16203946

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20180130905A1

公开(公告)日：2018-05-10

申请号：US15620631

申请日：2017-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun CHUNG ,  Jong Ho PARK ,  Seung Ha OH ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L21/324 ,  H01L21/283

CPC classification number: H01L29/7831 ,  B82Y10/00 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78696

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

公开(公告)号：US20220130884A1

公开(公告)日：2022-04-28

申请号：US17393855

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Shik KIM ,  Min-Sun KEEL ,  Hoon Joo NA ,  Kang Ho LEE ,  Kil Ho LEE ,  Sang Kil LEE ,  Jung Hyuk LEE ,  Shin Hee HAN

IPC: H01L27/146

Abstract: An image sensor including a variable resistance element is provided. The image sensor comprises first and second chips having first and second connecting structures; and a contact plug connecting the first and second chips. The first chip includes a photoelectric conversion element. The second chip includes a first variable resistance element. The contact plug extends from the first surface of the first semiconductor substrate to connect the first and second connecting structures.

公开(公告)号：US20180261677A1

公开(公告)日：2018-09-13

申请号：US15653588

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hoon LEE ,  Hyeon Jin KIM ,  Hoon Joo NA ,  Sung In SUH ,  Chan Hyeong LEE ,  Hu Yong LEE ,  Seong Hoon JEONG ,  Sang Jin HYUN

IPC: H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L21/28

Abstract: A semiconductor device includes a gate insulating layer disposed on a substrate, a first work function tuning layer disposed on the gate insulating layer, a lower barrier conductive layer on and in contact with the first work function tuning layer, and an upper barrier conductive layer on and in contact with the lower barrier conductive layer. The upper barrier conductive layer and the lower barrier conductive layer include a material in common, e.g., they may each include a titanium nitride (TiN) layer.

公开(公告)号：US20210013207A1

公开(公告)日：2021-01-14

申请号：US17038964

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20180069006A1

公开(公告)日：2018-03-08

申请号：US15452203

申请日：2017-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7845

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.