公开(公告)号：US20190109135A1

公开(公告)日：2019-04-11

申请号：US16203946

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20210013207A1

公开(公告)日：2021-01-14

申请号：US17038964

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.