公开(公告)号：US20230411498A1

公开(公告)日：2023-12-21

申请号：US18175821

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hee HAN ,  Bong Kwan BAEK ,  Sang Shin JANG ,  Koung Min RYU ,  Jong Min BAEK ,  Jung Hoo SHIN ,  Jun Hyuk LIM ,  Jung Hwan CHUN

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475

Abstract: A method for fabricating semiconductor device may include forming a source/drain pattern on a fin-type pattern, forming an etch stop film and an interlayer insulating film on the source/drain pattern, forming a contact hole in the interlayer insulating film, forming a sacrificial liner along a sidewall and a bottom surface of the contact hole, performing an ion implantation process while the sacrificial liner is present, removing the sacrificial liner and forming a contact liner along the sidewall of the contact hole, and forming a source/drain contact on the contact liner. The ion implantation process may include implant impurities into the source/drain pattern. The source/drain contact may be connected to the source/drain pattern.

公开(公告)号：US20200350429A1

公开(公告)日：2020-11-05

申请号：US16932076

申请日：2020-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Soo KIM ,  Dong Hyun ROH ,  Koung Min RYU ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

公开(公告)号：US20240194752A1

公开(公告)日：2024-06-13

申请号：US18502352

申请日：2023-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Sang Koo KANG ,  Jun Chae LEE ,  Koung Min RYU ,  Woo Jin LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first direction, gate electrodes covering the active pattern and extending in a second direction, a gate spacer disposed on a sidewall of each of the gate electrodes, a source/drain pattern disposed between adjacent ones of the gate electrodes, an etch stop film disposed along a sidewall of the gate spacer and a profile of the source/drain pattern, an interlayer insulating film disposed between the adjacent ones of the gate electrodes with a contact trench exposing the source/drain pattern defined therein, a liner film disposed on an outer sidewall of the contact trench, and a source/drain contact disposed on the liner film and filling the contact trench, in which the source/drain contact is connected to the source/drain pattern. At least a portion of the liner film may be disposed in the source/drain pattern.

公开(公告)号：US20240153948A1

公开(公告)日：2024-05-09

申请号：US18415863

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Gi Gwan PARK ,  Jung Hun CHOI ,  Koung Min RYU ,  Sun Jung LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5283 ,  H01L29/42364 ,  H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

公开(公告)号：US20250113597A1

公开(公告)日：2025-04-03

申请号：US18978581

申请日：2024-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Gi Gwan PARK ,  Jung Hun CHOI ,  Koung Min RYU ,  Sun Jung LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L27/092 ,  H01L29/423 ,  H01L29/739

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

公开(公告)号：US20240204107A1

公开(公告)日：2024-06-20

申请号：US18532230

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Koo KANG ,  Woo Kyung YOU ,  Min Jae KANG ,  Koung Min RYU ,  Hoon Seok SEO ,  Woo Jin LEE ,  Jun Chae LEE

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes: a substrate including an upper side and a lower side; first and second active patterns spaced apart from each other; a field insulating film covering side walls of the first and second active patterns; a power rail disposed adjacent to a first side wall of the second active pattern and between the first active pattern and the second active pattern; a power rail via disposed on the power rail and connected to the power rail; a semiconductor etching stop pattern disposed adjacent to a second side wall of the second active pattern; and a first semiconductor pattern disposed on the semiconductor etching stop pattern, wherein a lower surface of the semiconductor etching stop pattern is disposed on substantially a same plane as the lower side of the substrate, and wherein at least part of the first semiconductor pattern is disposed in the field insulating film.

公开(公告)号：US20170141107A1

公开(公告)日：2017-05-18

申请号：US15333545

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Gi Gwan PARK ,  Jung Hun CHOI ,  Koung Min RYU ,  Sun Jung LEE

IPC: H01L27/088 ,  H01L29/423 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.