公开(公告)号：US20170170268A1

公开(公告)日：2017-06-15

申请号：US15367320

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Peijie Feng ,  Kern Rim ,  Jeffrey Junhao Xu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L21/324 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/78696

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure having rounded nanowire structures is disclosed. To reduce the distance between adjacent nanowire structures to reduce parasitic capacitance while providing sufficient gate control of the channel, the nanowire channel structure employs rounded nanowire structures. For example, the rounded nanowire structures provide for a decreased height from a center area of the rounded nanowire structures to end areas of the rounded nanowire structures. Gate material is disposed around rounded ends of the rounded nanowire structures to extend into a portion of separation areas between adjacent nanowire structures. The gate material extends in the separation areas between adjacent nanowire structures sufficient to create a fringing field to the channel where gate material is not adjacently disposed, to provide strong gate control of the channel even though gate material does not completely surround the rounded nanowire structures.

公开(公告)号：US09660649B2

公开(公告)日：2017-05-23

申请号：US14639755

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: H03L5/00 ,  H03K19/00 ,  H03K19/0185 ,  G06F1/32 ,  G06F17/50

CPC classification number: H03K19/0016 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3296 ,  G06F17/505 ,  G06F2209/5019 ,  G06F2217/68 ,  G06F2217/78 ,  H03K19/018507 ,  Y02D10/172 ,  Y02D10/174

Abstract: A method for scaling voltages provided to different modules of a system-on-chip (SOC) includes receiving, at an energy-performance engine of the SOC, a first indication of usage history for a first module of the SOC and a second indication of usage history for a second module of the SOC. The method includes receiving a battery life indication that indicates a remaining battery life for a battery of the SOC. The method also includes adjusting a first supply voltage provided to the first module of the SOC based on the first indication, the second indication, and the battery life indication. The method further includes adjusting a second supply voltage provided to the second module of the SOC based on the first indication, the second indication, and the battery life indication.

公开(公告)号：US20170110374A1

公开(公告)日：2017-04-20

申请号：US15198763

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L21/823821 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/823431 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

公开(公告)号：US20170062439A1

公开(公告)日：2017-03-02

申请号：US15347530

申请日：2016-11-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  G11C11/419 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3213 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11

Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

Abstract translation: 一种装置包括耦合到位单元的第一金属层。 该装置还包括第三金属层，其包括耦合到位单元的写入字线。 该装置还包括在第一金属层和第三金属层之间的第二金属层。 第二金属层包括耦合到位单元的两个读字线。

公开(公告)号：US09564361B2

公开(公告)日：2017-02-07

申请号：US14026893

申请日：2013-09-13

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC: H01L21/768 ,  G06F17/50 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

Abstract translation: 在特定实施例中，一种方法包括形成与第一侧壁结构相邻并与半导体器件的心轴相邻的第二硬掩模层。 心轴的顶部在形成第二硬掩模层之前被暴露。 该方法还包括去除第一侧壁结构以暴露第一硬掩模层的第一部分。 该方法还包括蚀刻第一硬掩模层的第一部分以暴露电介质材料的第二部分。 该方法还包括蚀刻介电材料的第二部分以形成第一沟槽。 该方法还包括在第一沟槽内形成第一金属结构。

公开(公告)号：US09542518B2

公开(公告)日：2017-01-10

申请号：US14656426

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: G06F17/50 ,  G06F15/76

CPC classification number: G06F17/5045 ,  G06F15/76

Abstract: A method for designing a system-on-chip (SOC) for a wireless device includes receiving, at a design processor, first usage conditions for a first module of the SOC and second usage conditions for a second module of the SOC. The method further includes determining design parameters for the SOC. The design parameters are determined based on the first usage conditions and the second usage conditions.

Abstract translation: 一种用于设计用于无线设备的片上系统（SOC）的方法包括：在设计处理器处接收所述SOC的第一模块的第一使用条件和所述SOC的第二模块的第二使用条件。 该方法还包括确定SOC的设计参数。 基于第一使用条件和第二使用条件来确定设计参数。

公开(公告)号：US09502283B2

公开(公告)日：2016-11-22

申请号：US14627653

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang ,  Choh Fei Yeap

IPC: H01L21/768 ,  G06F17/50 ,  H01L21/311 ,  H01L23/535 ,  G03F1/00 ,  G03F7/20

CPC classification number: H01L21/76802 ,  G03F1/14 ,  G03F7/203 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/7045 ,  G03F7/70466 ,  G06F17/5077 ,  H01L21/31116 ,  H01L23/535

Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.

Abstract translation: 公开了基于电子束（e-beam）的半导体器件特征。 在特定方面，一种方法包括执行第一光刻工艺以在半导体器件上制造第一组切割图案特征。 从特征到有效区域的第一组切割图案特征的每个特征的距离大于或等于阈值距离。 该方法还包括执行电子束（e-beam）工艺以在半导体器件上制造第二切割图案特征。 第二切割图案特征从第二切割图案特征到有效区域的第二距离小于或等于阈值距离。

公开(公告)号：US20160247554A1

公开(公告)日：2016-08-25

申请号：US14631603

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Zhongze Wang ,  Xiaonan Chen ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/0407 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

Abstract translation: 一种装置包括静态随机存取存储器和被配置为发起与静态随机存取存储器相关联的校正动作的电路。 可以基于具有响应于静态随机存取存储器的加电的特定状态的多个静态随机存取存储器单元来启动校正动作。

公开(公告)号：US09424909B1

公开(公告)日：2016-08-23

申请号：US14659937

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/417 ,  G06F17/50 ,  G11C11/412

CPC classification number: G11C11/417 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/54 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

Abstract translation: 所公开的方面包括在多种操作模式下具有基本恒定的操作成品率的静态随机存取存储器（SRAM）阵列。 在一个方面，提供了一种设计具有多种模式操作的SRAM阵列的方法。 该方法包括确定与每个操作模式相关联的性能特征。 配置为在每个操作模式下操作的SRAM位单元被提供给SRAM阵列。 SRAM位单元被偏置以在使用动态自适应辅助技术的操作模式下操作，其中SRAM位单元在整个模式下实现基本上恒定的运行产量。 SRAM位单元具有相应的类型，其中方法中的SRAM位单元类型的数量小于操作模式的数量。 因此，每个SRAM阵列可以实现特定的操作模式，而不需要用于每个模式的单独的SRAM位单元类型，从而降低成本。

公开(公告)号：US20160225767A1

公开(公告)日：2016-08-04

申请号：US14611090

申请日：2015-01-30

Applicant: QUALCOMM INCORPORATED

Inventor： Yanxiang Liu ,  Stanley Seungchul Song

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207 ,  H01L29/0847

Abstract: A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.

Abstract translation: 半导体器件包括扩散区域，耦合到扩散区域的栅极结构以及耦合到扩散区域的虚拟栅极结构。 栅极结构延伸超过扩散区域的第一距离，并且虚拟栅极结构延伸超过扩散区域的第二距离。