公开(公告)号：US09905670B2

公开(公告)日：2018-02-27

申请号：US14742336

申请日：2015-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsuan Lin ,  Chih-Wei Chang

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/477 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/477 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795

Abstract: A method includes performing a first sputtering to form a first metal film on a surface of a semiconductor region. The first sputtering is performed using a first ion energy. The method further includes performing a second sputtering to form a second metal film over and contacting the first metal film, wherein the first and the second metal films includes a same metal. The second sputtering is performed using a second ion energy lower than the first ion energy. An annealing is performed to react the first and the second metal films with the semiconductor region to form a metal silicide.

公开(公告)号：US20180040664A1

公开(公告)日：2018-02-08

申请号：US15788695

申请日：2017-10-19

Applicant: Renesas Electronics Corporation

Inventor： Takeshi Kamino ,  Takahiro Tomimatsu

IPC: H01L27/146 ,  H01L21/28 ,  H01L21/266 ,  H01L21/285 ,  H04N5/374 ,  H01L29/66

CPC classification number: H01L27/14689 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/28518 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14685 ,  H01L29/665 ,  H04N5/374

Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.

公开(公告)号：US09887302B2

公开(公告)日：2018-02-06

申请号：US15346501

申请日：2016-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chieh-Chih Chou ,  Chih-Wen Hsiung ,  Kong-Beng Thei

IPC: H01L29/872 ,  H01L21/225 ,  H01L21/265 ,  H01L21/285 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L29/872 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/66143

Abstract: A Schottky barrier diode is provided, which includes a semiconductor substrate, a first well region, an isolation region, a silicide layer and a silicon oxide-containing layer. The first well region of a first conductivity type is in the semiconductor substrate. The isolation region is in the first well region. The silicide layer is laterally adjacent to the isolation region, and over and in contact with the first well region. The silicon oxide-containing layer is over and in contact with the isolation region.

公开(公告)号：US09887193B2

公开(公告)日：2018-02-06

申请号：US15212131

申请日：2016-07-15

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/285

CPC classification number: H01L21/823456 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/535 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.

公开(公告)号：US09887129B2

公开(公告)日：2018-02-06

申请号：US14477689

申请日：2014-09-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/94 ,  H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US20180033687A1

公开(公告)日：2018-02-01

申请号：US15223902

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu HUNG ,  Sung-Li WANG ,  Pei-Wen WU ,  Yida LI ,  Chih-Wei CHANG ,  Huang-Yi HUANG ,  Cheng-Tung LIN ,  Jyh-Cherng SHEU ,  Yee-Chia YEO ,  Chi-On CHUI

IPC: H01L21/768

CPC classification number: H01L21/76856 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.

公开(公告)号：US09876094B2

公开(公告)日：2018-01-23

申请号：US14984037

申请日：2015-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok-Han Bae ,  Kyung-Soo Kim ,  Chul-Sung Kim ,  Woo-Cheol Shin ,  Hwi-Chan Jun

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/285 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/823418 ,  H01L21/823437 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.

公开(公告)号：US09859384B2

公开(公告)日：2018-01-02

申请号：US15431807

申请日：2017-02-14

Applicant: International Business Machines Corporation

Inventor： Hari V. Mallela ,  Robert R. Robison ,  Reinaldo Vega ,  Rajasekhar Venigalla

IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/80 ,  H01L29/94 ,  H01L29/417 ,  H01L29/78 ,  H01L23/485

CPC classification number: H01L29/41741 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/78696

Abstract: Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.

公开(公告)号：US09853156B2

公开(公告)日：2017-12-26

申请号：US14618414

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Subhash M. Joshi ,  Jin-Sung Chun

IPC: H01L29/78 ,  H01L21/02 ,  H01L23/48 ,  H01L29/66 ,  H01L29/417 ,  H01L21/283 ,  H01L21/3205 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L29/785 ,  H01L21/02 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/48 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

公开(公告)号：US20170365523A1

公开(公告)日：2017-12-21

申请号：US15674185

申请日：2017-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon JEONG ,  Jae Yup CHUNG ,  Heesoo KANG ,  Donghyun KIM ,  Sanghyuk HONG ,  Soohun HONG

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7855

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.