公开(公告)号：US10049964B2

公开(公告)日：2018-08-14

申请号：US14061244

申请日：2013-10-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

公开(公告)号：US09893017B2

公开(公告)日：2018-02-13

申请号：US15089151

申请日：2016-04-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Pandi C. Marimuthu ,  Yaojian Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/85005 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.

公开(公告)号：US09620413B2

公开(公告)日：2017-04-11

申请号：US14097534

申请日：2013-12-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Thomas J. Strothmann ,  Damien M. Pricolo ,  Il Kwon Shim ,  Yaojian Lin ,  Heinz-Peter Wirtz ,  Seung Wook Yoon ,  Pandi C. Marimuthu

IPC: H01L21/78 ,  H01L23/28 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L24/12 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/951 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

公开(公告)号：US20150348936A1

公开(公告)日：2015-12-03

申请号：US14721677

申请日：2015-05-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

Abstract translation: 半导体器件具有第一部件。 模块化互连结构被布置成与第一部件相邻。 在第一组件和模块化互连结构上形成第一互连结构。 在第一组件，模块化互连结构和第一互连结构上形成屏蔽层。 屏蔽层为封闭的半导体器件提供防止EMI，RFI或其他器件间干扰的保护，无论是内部产生还是从外部半导体器件产生。 屏蔽层电连接到外部低阻抗接地点。 第二部件邻近第一部件设置。 第二组件包括无源设备。 LC电路包括第一部件和第二部件。 将半导体管芯设置成与第一部件相邻。 导电粘合剂设置在模块化互连结构之上。 模块化互连结构包括小于第一部件的高度的高度。

公开(公告)号：US09184139B2

公开(公告)日：2015-11-10

申请号：US14109313

申请日：2013-12-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate including a base substrate material and a plurality of conductive vias formed partially though the substrate. A plurality of semiconductor die including a base semiconductor material is disposed over the substrate. A ratio of an encapsulant to a quantity of the semiconductor die is determined for providing structural support for the semiconductor die. An encapsulant is deposited over the semiconductor die and substrate. An amount of the encapsulant is selected based on the determined ratio or based on a total amount of the base substrate material and base semiconductor material. Channels are formed in the encapsulant by removing a portion of the encapsulant in a peripheral region of the semiconductor die. Alternatively, a side surface of the semiconductor die is partially exposed with respect to the encapsulant. A portion of the base substrate material is removed to expose the conductive vias.

Abstract translation: 半导体器件具有包括基底材料和部分地通过衬底形成的多个导电通孔的衬底。 包括基底半导体材料的多个半导体管芯设置在基板上。 确定密封剂与半导体管芯的量的比率以提供半导体管芯的结构支撑。 密封剂沉积在半导体管芯和衬底上。 基于确定的比例或基于基底材料和基底半导体材料的总量来选择一定量的密封剂。 通过在半导体管芯的周边区域中去除一部分密封剂而在密封剂中形成通道。 或者，半导体管芯的侧表面相对于密封剂部分地露出。 去除基底衬底材料的一部分以露出导电通孔。

公开(公告)号：US20150054151A1

公开(公告)日：2015-02-26

申请号：US14503698

申请日：2014-10-01

Applicant: STATS CHIPPAC, LTD.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11822 ,  H01L2224/11906 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Abstract translation: 半导体器件具有半导体管芯，其具有形成在管芯上的第一导电层。 第一绝缘层形成在管芯上方，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 通过在第一绝缘层上形成第二绝缘层，其宽度小于第一开口的第二开口并将导电材料沉积到第二开口中来构造互连结构。 互连结构可以是导电柱或导电垫。 互连结构的宽度小于第一开口的宽度。 除去第一开口外部的第一绝缘层上的第二导电层，同时将第二导电层留在互连结构下。

公开(公告)号：US20140183718A1

公开(公告)日：2014-07-03

申请号：US14036525

申请日：2013-09-25

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L21/78 ,  H01L23/31

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.

Abstract translation: 半导体器件包括标准化载体。 半导体晶片包括多个半导体管芯和基底半导体材料。 半导体晶片通过基极半导体材料的第一部分被分离，以分离半导体晶粒。 半导体管芯设置在标准化载体上。 标准化载体的尺寸与半导体管芯的尺寸无关。 密封剂沉积在标准化载体上并围绕半导体管芯。 在半导体管芯上形成互连结构，同时留下没有互连结构的密封剂。 半导体器件通过密封剂分离。 密封剂保持设置在半导体管芯的一侧。 或者，半导体器件通过基极半导体的第二部分并通过密封剂被切割，以从半导体管芯的侧面去除基极半导体和密封剂的第二部分。

公开(公告)号：US20140175640A1

公开(公告)日：2014-06-26

申请号：US14039092

申请日：2013-09-27

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HunTeak Lee ,  HeeJo Chi

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

Abstract translation: 半导体器件具有设置在载体上的多个半导体管芯。 在半导体管芯上方形成诸如柱形凸块的电互连。 螺柱凸块被修剪成均匀的高度。 衬底包括在衬底上的凸块。 将半导体管芯的电气互连结合到衬底的凸块上，同时将半导体管芯设置在载体上。 在半导体管芯和衬底之间沉积底部填充材料。 或者，使用追逐模具在半导体管芯和衬底上沉积密封剂。 半导体管芯的凸起凸块与衬底的凸起的接合是使用回流焊或热压而进行的，同时半导体管芯是重新构成的晶片形式并且附着到载体上，以提供与衬底的倒装芯片型互连的高通量。

公开(公告)号：US20140077389A1

公开(公告)日：2014-03-20

申请号：US13800807

申请日：2013-03-13

Applicant: STATS CHIPPAC, LTD.

Inventor： Il Kwon Shim ,  Jun Mo Koo ,  Pandi C. Marimuthu ,  Yaojian Lin ,  See Chian Lim

IPC: H01L23/48 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.

Abstract translation: 半导体器件具有包括基底和从基底延伸的多个导电柱的基底。 衬底可以是晶片形状，面板或单体形式。 导电柱可以具有圆形，矩形，锥形或变窄的中间形状。 通过导电柱之间的底座中的开口设置半导体管芯。 半导体管芯延伸到导电柱之上，或者设置在导电柱的下方。 密封剂沉积在半导体管芯上并且在导电柱周围。 去除基底和一部分密封剂以电绝缘导电柱。 在半导体管芯，密封剂和导电柱之上形成互连结构。 在半导体管芯，密封剂和导电柱上形成绝缘层。 半导体封装设置在半导体管芯上并电连接到导电柱。

公开(公告)号：US20140077364A1

公开(公告)日：2014-03-20

申请号：US13832781

申请日：2013-03-15

Applicant: STATS CHIPPAC, LTD.

Inventor： Pandi C. Marimuthu ,  Sheila Marie L. Alvarez ,  Yaojian Lin ,  Jose A. Caparas ,  Yang Kern Jonathan Tan

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/2633 ,  H01L21/311 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/02311 ,  H01L2224/02379 ,  H01L2224/0558 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49174 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/94 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Abstract translation: 半导体器件具有设置在衬底的第一表面上的衬底和半导体管芯。 线柱附接到基底的第一表面。 线螺柱包括基部和杆部。 在衬底的第二表面上形成焊盘。 密封剂沉积在衬底，半导体管芯和线螺柱上。 密封剂的一部分被LDA去除以暴露线螺柱。 通过LDA去除一部分密封剂以暴露基底。 互连结构形成在密封剂上并电连接到线芯和半导体管芯。 在互连结构上形成凸点。 半导体封装设置在密封剂上并电连接到衬底。 分立半导体器件设置在密封剂上并电连接到衬底。