公开(公告)号：US20150348936A1

公开(公告)日：2015-12-03

申请号：US14721677

申请日：2015-05-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

Abstract translation: 半导体器件具有第一部件。 模块化互连结构被布置成与第一部件相邻。 在第一组件和模块化互连结构上形成第一互连结构。 在第一组件，模块化互连结构和第一互连结构上形成屏蔽层。 屏蔽层为封闭的半导体器件提供防止EMI，RFI或其他器件间干扰的保护，无论是内部产生还是从外部半导体器件产生。 屏蔽层电连接到外部低阻抗接地点。 第二部件邻近第一部件设置。 第二组件包括无源设备。 LC电路包括第一部件和第二部件。 将半导体管芯设置成与第一部件相邻。 导电粘合剂设置在模块化互连结构之上。 模块化互连结构包括小于第一部件的高度的高度。

公开(公告)号：US20140183718A1

公开(公告)日：2014-07-03

申请号：US14036525

申请日：2013-09-25

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L21/78 ,  H01L23/31

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.

Abstract translation: 半导体器件包括标准化载体。 半导体晶片包括多个半导体管芯和基底半导体材料。 半导体晶片通过基极半导体材料的第一部分被分离，以分离半导体晶粒。 半导体管芯设置在标准化载体上。 标准化载体的尺寸与半导体管芯的尺寸无关。 密封剂沉积在标准化载体上并围绕半导体管芯。 在半导体管芯上形成互连结构，同时留下没有互连结构的密封剂。 半导体器件通过密封剂分离。 密封剂保持设置在半导体管芯的一侧。 或者，半导体器件通过基极半导体的第二部分并通过密封剂被切割，以从半导体管芯的侧面去除基极半导体和密封剂的第二部分。

公开(公告)号：US20130221452A1

公开(公告)日：2013-08-29

申请号：US13853969

申请日：2013-03-29

Applicant: Stats ChipPAC, Ltd.

Inventor： Thomas J. Strothmann ,  Steve Anderson ,  Byung Joon Han ,  Il Kwon Shim ,  Heap Hoe Kuan

IPC: H01L29/66 ,  H01L21/56

CPC classification number: H01L29/66 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 可以在密封剂和半导体管芯上方形成导电层。 可以在半导体管芯上形成透射层。 可以通过密封剂形成互连结构并且电连接到导电层，由此互连结构仅形成在半导体管芯的仅一侧。

公开(公告)号：US09754897B2

公开(公告)日：2017-09-05

申请号：US14721677

申请日：2015-05-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Byung Joon Han ,  Rajendra D. Pendse ,  Il Kwon Shim ,  Pandi C. Marimuthu ,  Won Kyoung Choi ,  Linda Pei Ee Chua

IPC: H04L23/00 ,  H01L23/552 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component.

公开(公告)号：US09704824B2

公开(公告)日：2017-07-11

申请号：US14070509

申请日：2013-11-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim ,  Byung Joon Han

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

公开(公告)号：US09553162B2

公开(公告)日：2017-01-24

申请号：US13853969

申请日：2013-03-29

Applicant: STATS ChipPAC, Ltd.

Inventor： Thomas J. Strothmann ,  Steve Anderson ,  Byung Joon Han ,  Il Kwon Shim ,  Heap Hoe Kuan

IPC: H01L29/66 ,  H01L21/56 ,  H01L23/00 ,  H01L27/146 ,  H01L23/31

CPC classification number: H01L29/66 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 可以在密封剂和半导体管芯上方形成导电层。 可以在半导体管芯上形成透射层。 可以通过密封剂形成互连结构并且电连接到导电层，由此互连结构仅形成在半导体管芯的仅一侧。

公开(公告)号：US20140183761A1

公开(公告)日：2014-07-03

申请号：US14070509

申请日：2013-11-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim ,  Byung Joon Han

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

Abstract translation: 半导体器件包括沉积在半导体管芯上方和周围的半导体管芯和密封剂。 半导体晶片包括多个半导体管芯和基底半导体材料。 在基底半导体材料中形成凹槽。 半导体晶片通过沟槽分离，以分离半导体管芯。 将半导体管芯设置在半导体管芯之间的距离为500微米（μm）以下的载体上。 密封剂覆盖半导体管芯的侧壁。 在半导体管芯上形成扇形互连结构，而密封剂保持没有扇形互连结构。 密封剂的一部分从半导体管芯的非活性表面去除。 通过密封剂将器件分离，同时留下覆盖半导体管芯侧壁的密封剂。 覆盖侧壁的密封剂的厚度为50μm以下。

公开(公告)号：US09721862B2

公开(公告)日：2017-08-01

申请号：US14036525

申请日：2013-09-25

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.