公开(公告)号：US09553162B2

公开(公告)日：2017-01-24

申请号：US13853969

申请日：2013-03-29

Applicant: STATS ChipPAC, Ltd.

Inventor： Thomas J. Strothmann ,  Steve Anderson ,  Byung Joon Han ,  Il Kwon Shim ,  Heap Hoe Kuan

IPC: H01L29/66 ,  H01L21/56 ,  H01L23/00 ,  H01L27/146 ,  H01L23/31

CPC classification number: H01L29/66 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 可以在密封剂和半导体管芯上方形成导电层。 可以在半导体管芯上形成透射层。 可以通过密封剂形成互连结构并且电连接到导电层，由此互连结构仅形成在半导体管芯的仅一侧。

公开(公告)号：US09524938B2

公开(公告)日：2016-12-20

申请号：US13845409

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Heap Hoe Kuan ,  Seng Guan Chow

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/5384 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68372 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

公开(公告)号：US09406647B2

公开(公告)日：2016-08-02

申请号：US14214120

申请日：2014-03-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Heap Hoe Kuan

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/97 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/498 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/20 ,  H01L2224/96 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract translation: 半导体器件首先通过锯切街道引导件提供晶片，并且具有形成在晶片的有效表面上的接合焊盘。 晶片用切割胶带胶带。 将晶片沿着锯条导轨分割为具有在多个模具中的每一个之间具有多个间隙的多个模具。 切割带被拉伸以将多个间隙扩展到预定距离。 有机材料沉积在多个间隙中的每一个中。 有机材料的顶表面与多个管芯的第一管芯的顶表面基本共面。 重分布层在有机材料的一部分上被图案化。 凹凸金属化（UBM）通过再分配层与接合焊盘电连接在有机材料上沉积。

公开(公告)号：US20140127858A1

公开(公告)日：2014-05-08

申请号：US14154049

申请日：2014-01-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Abstract translation: 嵌入式半导体管芯封装通过使用粘合剂将框架载体安装到临时载体上而制成。 框架载体包括每个包括围绕腔的引线框架互连结构的管芯安装位置。 半导体管芯设置在每个腔中。 将密封剂沉积在模具上的空腔中。 封装互连结构形成在引线框架互连结构和密封剂上。 封装互连结构和引线框互连结构电连接到管芯。 帧载体被分成单独的嵌入式芯片封装。 半导体管芯可以垂直堆叠或并排放置在腔内。 嵌入式管芯封装可以通过引线框互连结构堆叠并电互连。 半导体器件可以安装到嵌入式裸片封装并且通过引线框互连结构电连接到裸片。

公开(公告)号：US09515016B2

公开(公告)日：2016-12-06

申请号：US13682281

申请日：2012-11-20

Applicant: STATS ChipPAC, Ltd.

Inventor： Rui Huang ,  Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/683 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.

Abstract translation: 使用包括基板和多个导电柱的预制柱载体制成半导体封装。 胶片密封剂设置在柱载体的基板上并且在导电柱周围。 半导体管芯安装到临时载体上。 将载体和临时载体压在一起以将半导体管芯嵌入膜密封剂中。 半导体管芯设置在膜密封剂中的导电柱之间。 卸载载体的临时载体和基板。 在膜密封剂的第一侧上形成第一电路堆积层。 第一电路堆积层电连接到导电柱。 第二电路堆积层形成在与第一侧相对的膜密封剂的第二侧上。 第二电路堆积层电连接到导电柱。

公开(公告)号：US09059186B2

公开(公告)日：2015-06-16

申请号：US14154049

申请日：2014-01-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC: H01L21/4763 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Abstract translation: 嵌入式半导体管芯封装通过使用粘合剂将框架载体安装到临时载体上而制成。 框架载体包括每个包括围绕腔的引线框架互连结构的管芯安装位置。 半导体管芯设置在每个腔中。 将密封剂沉积在模具上的空腔中。 封装互连结构形成在引线框架互连结构和密封剂上。 封装互连结构和引线框互连结构电连接到管芯。 帧载体被分成单独的嵌入式芯片封装。 半导体管芯可以垂直堆叠或并排放置在腔内。 嵌入式管芯封装可以通过引线框互连结构堆叠并电互连。 半导体器件可以安装到嵌入式裸片封装并且通过引线框互连结构电连接到裸片。

公开(公告)号：US20130221452A1

公开(公告)日：2013-08-29

申请号：US13853969

申请日：2013-03-29

Applicant: Stats ChipPAC, Ltd.

Inventor： Thomas J. Strothmann ,  Steve Anderson ,  Byung Joon Han ,  Il Kwon Shim ,  Heap Hoe Kuan

IPC: H01L29/66 ,  H01L21/56

CPC classification number: H01L29/66 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 可以在密封剂和半导体管芯上方形成导电层。 可以在半导体管芯上形成透射层。 可以通过密封剂形成互连结构并且电连接到导电层，由此互连结构仅形成在半导体管芯的仅一侧。

公开(公告)号：US20130214385A1

公开(公告)日：2013-08-22

申请号：US13845409

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Heap Hoe Kuan ,  Seng Guan Chow

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68372 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Abstract translation: 半导体器件包括具有顶部，底部和外围表面的第一裸片。 在顶表面上形成接合垫。 有机材料连接到第一模具并围绕周边表面设置。 在有机材料中形成通孔。 金属迹线将通孔连接到接合垫。 导电材料沉积在通孔中。 再分布层（RDL）具有设置在第一管芯的顶表面上的互连焊盘。

公开(公告)号：US20140197540A1

公开(公告)日：2014-07-17

申请号：US14214120

申请日：2014-03-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Heap Hoe Kuan

IPC: H01L23/00

CPC classification number: H01L24/97 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/498 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/20 ,  H01L2224/96 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract translation: 半导体器件首先通过锯切街道引导件提供晶片，并且具有形成在晶片的有效表面上的接合焊盘。 晶片用切割胶带胶带。 将晶片沿着锯条导轨分割为具有在多个模具中的每一个之间具有多个间隙的多个模具。 切割带被拉伸以将多个间隙扩展到预定距离。 有机材料沉积在多个间隙中的每一个中。 有机材料的顶表面与多个管芯的第一管芯的顶表面基本共面。 重分布层在有机材料的一部分上被图案化。 凹凸金属化（UBM）通过再分配层与接合焊盘电连接在有机材料上沉积。

公开(公告)号：US20130075902A1

公开(公告)日：2013-03-28

申请号：US13683884

申请日：2012-11-21

Applicant: STATS CHIPPAC, LTD.

Inventor： Seng Guan Chow ,  Il Kwon Shim ,  Heap Hoe Kuan ,  Rui Huang

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts.

Abstract translation: 半导体封装包括具有基板和多个导电柱的柱载体。 光敏密封剂沉积在柱载体的基板上并且在导电柱周围。 蚀刻光敏密封剂以暴露柱载体的基板的一部分。 在光敏密封剂的蚀刻部分内的半导体管芯安装到柱载体的基板上。 第二密封剂沉积在半导体管芯上。 在第二密封剂上形成第一电路堆积层。 第一电路堆积层电连接到导电柱。 去除柱载体的基板，并且在半导体管芯上形成第二电路堆积层，并且与第一电路堆积层相对的光敏封装体形成第二电路堆积层。 第二电路堆积层电连接到导电柱。