公开(公告)号：US20200312956A1

公开(公告)日：2020-10-01

申请号：US16365642

申请日：2019-03-26

Applicant: International Business Machines Corporation

Inventor： Chun-chen Yeh ,  Alexander Reznicek ,  Veeraraghavan S. Basker ,  Junli Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/04 ,  H01L29/78

Abstract: Self-limiting cavities are formed within a crystalline semiconductor substrate and beneath a stack of semiconductor layers used to form a nanosheet transistor device. Inner ends of the cavities merge beneath the stack while the outer ends thereof adjoin isolation regions within the substrate. The cavities are filled with electrically insulating material to provide bottom device isolation. Source/drain regions are grown in vertical trenches extending through the stack of semiconductor layers following formation of dielectric inner spacers. The bottom ends of the trenches adjoin the electrically insulating material within the cavities.

公开(公告)号：US10388768B2

公开(公告)日：2019-08-20

申请号：US15815616

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： Miaomiao Wang ,  Tenko Yamashita ,  Chun-chen Yeh ,  Hui Zang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L21/8234

Abstract: In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate. The recess is filled at least partially with a first conductive material. The first conductive material is insulated from the gate. The fin is replaced with a replacement structure. The replacement structure is electrically connected to the first conductive material using a second conductive material. the second conductive material is insulated from a first surface of the finFET. A first electrical contact structure is fabricated on the first surface. A second electrical contact structure is fabricated on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.

公开(公告)号：US10332961B2

公开(公告)日：2019-06-25

申请号：US15826841

申请日：2017-11-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/306 ,  B82Y10/00 ,  H01L29/775

Abstract: Embodiments are directed to a method of fabricating inner spacers of a nanosheet FET. The method includes forming sacrificial and channel nanosheets over a substrate, removing sidewall portions of the sacrificial nanosheet, and forming a dielectric that extends over the channel nanosheet and within a space that was occupied by the removed sidewall portions of the sacrificial nanosheet. The method further includes forming a top protective spacer over the channel nanosheet and the dielectric, as well as applying a directional etch to the top protective spacer, the channel nanosheet, and the dielectric, wherein the directional etch is configured to be selective to the channel nanosheet and the dielectric, wherein the directional etch is configured to not be selective to the top protective spacer, and wherein applying the directional etch etches portions of the channel nanosheet and portions of the flowable dielectric that are not under the top dielectric.

公开(公告)号：US20190181012A1

公开(公告)日：2019-06-13

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/24 ,  H01L21/768 ,  H01L29/08 ,  H01L29/78 ,  H01L29/267

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US10276573B2

公开(公告)日：2019-04-30

申请号：US15168382

申请日：2016-05-31

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/06 ,  H01L21/308 ,  H01L21/033 ,  H01L29/78 ,  H01L29/165 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

公开(公告)号：US09887196B2

公开(公告)日：2018-02-06

申请号：US14583842

申请日：2014-12-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L27/092 ,  H01L29/10 ,  H01L27/12 ,  H01L21/84 ,  H01L29/165 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/06 ,  H01L21/033 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/7849

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

公开(公告)号：US09853158B2

公开(公告)日：2017-12-26

申请号：US15198801

申请日：2016-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02694 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/66818

Abstract: Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin.

公开(公告)号：US09685555B2

公开(公告)日：2017-06-20

申请号：US14584161

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Nicolas Loubet ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/7856 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/0657 ,  H01L29/4975 ,  H01L29/6681 ,  H01L2029/7858

Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.

公开(公告)号：US20170077264A1

公开(公告)日：2017-03-16

申请号：US15337225

申请日：2016-10-28

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0226 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

Abstract translation: 提供了形成紧密堆积的混合纳米线的技术。 一方面，用于形成混合纳米线的方法包括：在基板上的叠层中形成第一和第二材料的交替层; 在堆叠中形成第一沟槽和第二沟槽; 在所述第一沟槽内横向蚀刻所述第二材料的层以在所述层中形成第一空腔; 在填充第一空腔的第一沟槽内生长第一外延材料; 在所述第二沟槽内横向蚀刻所述第二材料的层以在所述层中形成第二空腔; 在填充第二空腔的第二沟槽内生长第二外延材料，其中第一空腔中的第一外延材料和第二空腔中的第二外延材料是混合纳米线。 还提供了纳米线FET器件及其形成方法。

公开(公告)号：US09431540B2

公开(公告)日：2016-08-30

申请号：US14288766

申请日：2014-05-28

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。