公开(公告)号：US09006802B2

公开(公告)日：2015-04-14

申请号：US13212834

申请日：2011-08-18

Applicant: Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

Inventor： Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02274 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/324 ,  H01L29/66795

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Abstract translation: 公开了形成绝缘材料层的半导体器件制造方法和方法。 在一个实施例中，形成半导体器件的复合绝缘材料层的方法包括提供工件并使用第一等离子体功率电平在工件上形成绝缘材料层的第一子层。 使用第二等离子体功率电平在绝缘材料层的第一子层上形成绝缘材料层的第二子层，并且将工件退火。

公开(公告)号：US20120068268A1

公开(公告)日：2012-03-22

申请号：US12888351

申请日：2010-09-22

Applicant: Tsai-Fu Hsiao ,  Tsuo-Wen Lu ,  Yu-Ren Wang

Inventor： Tsai-Fu Hsiao ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method of fabricating a transistor structure includes the step of providing a substrate having a gate thereon. Then, a first spacer is formed at two sides of the gate. After that, an LDD region is formed in the substrate at two sides of the gate. Later, a second spacer comprising a carbon-containing spacer and a sacrificing spacer is formed on the first spacer. Subsequently, a source/drain region is formed in the substrate at two sides of the gate. Finally, the sacrificing spacer is removed entirely, and part of the carbon-containing spacer is also removed. The remaining carbon-containing spacer has an L shape. The carbon-containing spacer has a first carbon concentration, and the sacrificing spacer has a second carbon concentration. The first carbon concentration is greater than the second carbon concentration.

Abstract translation: 制造晶体管结构的方法包括提供其上具有栅极的衬底的步骤。 然后，在栅极的两侧形成第一间隔物。 之后，在栅极两侧的基板上形成LDD区域。 之后，在第一间隔物上形成包含含碳间隔物和牺牲间隔物的第二间隔物。 随后，在栅极两侧的基板中形成源/漏区。 最后，完全除去牺牲间隔物，并且还除去部分含碳间隔物。 剩余的含碳隔离物具有L形。 含碳隔离物具有第一碳浓度，牺牲间隔物具有第二碳浓度。 第一个碳浓度大于第二个碳浓度。

公开(公告)号：US20100001317A1

公开(公告)日：2010-01-07

申请号：US12168062

申请日：2008-07-03

Applicant: Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。

公开(公告)号：US20080132023A1

公开(公告)日：2008-06-05

申请号：US11564850

申请日：2006-11-30

Applicant: Yi-Wei Chen ,  Chao-Ching Hsieh ,  Tsai-Fu Hsiao ,  Yu-Lan Chang ,  Tsung-Yu Hung ,  Chun-Chieh Chang

Inventor： Yi-Wei Chen ,  Chao-Ching Hsieh ,  Tsai-Fu Hsiao ,  Yu-Lan Chang ,  Tsung-Yu Hung ,  Chun-Chieh Chang

IPC: H01L21/71 ,  H01L21/04

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66575

Abstract: A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.

Abstract translation: 提供半导体工艺。 半导体工艺包括提供衬底。 然后，对基板进行表面处理，以在基板上形成缓冲层。 接下来，对基板进行第一预非晶态注入。

公开(公告)号：US20070228464A1

公开(公告)日：2007-10-04

申请号：US11748479

申请日：2007-05-14

Applicant: Hsiang-Ying Wang ,  Chin-Cheng Chien ,  Tsai-Fu Hsiao ,  Ming-Yen Chien ,  Chao-Chun Chen

Inventor： Hsiang-Ying Wang ,  Chin-Cheng Chien ,  Tsai-Fu Hsiao ,  Ming-Yen Chien ,  Chao-Chun Chen

IPC: H01L29/772

CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L29/6659

Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.

Abstract translation: 一种形成MOS晶体管的方法，其中执行共注入以将注入植入源区域和漏区域或晕圈注入区域中，以有效地防止掺杂剂在源区和漏区中的过度扩散或 用于获得良好的接合曲线并改善短沟道效应。 植入物包括碳，烃或烃的衍生物，例如选自C，C≡H，H +和/或C（C） 其中x为1〜10的数，y为4〜20的数，n为1〜10的数，n为0〜 数量为1〜1000。

公开(公告)号：US20120052644A1

公开(公告)日：2012-03-01

申请号：US12868739

申请日：2010-08-26

Applicant: Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834

Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

Abstract translation: 本发明公开了一种制造MOS晶体管的方法。 提供其上具有栅极结构的基板。 氮化硅层沉积在栅极结构上。 然后执行干蚀刻工艺以在栅极结构的每个侧壁上限定氮化硅间隔物，并且在栅极结构的每一侧上的源极/漏极区域中形成凹陷。 沉积覆盖栅极结构和凹陷的过渡层。 执行预外延清洁处理以去除过渡层。 对基板进行预烘烤处理。 进行外延生长工艺以在凹槽中生长嵌入的SiGe层。 去除一次性氮化硅间隔物。

公开(公告)号：US08076210B2

公开(公告)日：2011-12-13

申请号：US13043443

申请日：2011-03-08

Applicant: Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

Inventor： Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

IPC: H01L21/336

CPC classification number: H01L21/324 ,  H01L21/265 ,  H01L21/2652 ,  H01L29/6659

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.

Abstract translation: 公开了一种制造金属氧化物半导体晶体管的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成栅极结构; 以及执行第一离子注入工艺以在所述栅极结构的两侧将具有碳，硼和氢的第一分子簇注入到所述半导体衬底中，以形成掺杂区域，其中所述第一分子簇的分子量大于100 。

公开(公告)号：US07927954B2

公开(公告)日：2011-04-19

申请号：US11678627

申请日：2007-02-26

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

Abstract translation: 公开了制造应变硅晶体管的方法。 首先，提供半导体衬底，并且在半导体衬底上设置栅极结构和围绕栅极结构的间隔物。 然后在隔离物周围的半导体衬底中形成源极/漏极区域，并且执行第一快速热退火处理以激活源极/漏极区域内的掺杂剂。 执行蚀刻工艺以在栅极结构周围形成凹陷，并且执行选择性外延生长工艺以在凹部中形成外延层。 执行第二快速热退火处理以重新定义源/漏区域内的掺杂剂的分布并修复掺杂剂的损坏的键。

公开(公告)号：US07553763B2

公开(公告)日：2009-06-30

申请号：US11463012

申请日：2006-08-08

Applicant: Tsai-Fu Hsiao ,  Chin-Cheng Chien ,  Kuo-Tai Huang

Inventor： Tsai-Fu Hsiao ,  Chin-Cheng Chien ,  Kuo-Tai Huang

IPC: H01L21/20

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6656

Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.

Abstract translation: 自对准硅化物工艺包括提供包括至少预定的自对准硅化物区域的硅衬底，进行聚簇离子注入工艺以在硅衬底的预定自对准硅化物区域中形成非晶化层，在非晶化层的表面上形成金属层 并使金属层与非晶化层反应，以在硅衬底的表面上形成硅化物层。

公开(公告)号：US07473606B2

公开(公告)日：2009-01-06

申请号：US11675091

申请日：2007-02-15

Applicant: Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

Inventor： Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

IPC: H01L21/336 ,  H01L21/425 ,  H01L21/42

CPC classification number: H01L21/324 ,  H01L21/265 ,  H01L21/2652 ,  H01L29/6659

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.

Abstract translation: 公开了一种制造金属氧化物半导体晶体管的方法。 首先，提供其上具有栅极结构的半导体衬底，并且在栅极结构周围形成间隔物。 执行离子注入工艺以将包含硼的分子簇注入围绕间隔物的半导体衬底中，以形成源/漏区。 分子簇内各硼原子的重量比优选小于10％。 此后，执行毫秒退火处理以激活源极/漏极区域内的分子簇。