公开(公告)号：US20120052644A1

公开(公告)日：2012-03-01

申请号：US12868739

申请日：2010-08-26

Applicant: Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834

Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

Abstract translation: 本发明公开了一种制造MOS晶体管的方法。 提供其上具有栅极结构的基板。 氮化硅层沉积在栅极结构上。 然后执行干蚀刻工艺以在栅极结构的每个侧壁上限定氮化硅间隔物，并且在栅极结构的每一侧上的源极/漏极区域中形成凹陷。 沉积覆盖栅极结构和凹陷的过渡层。 执行预外延清洁处理以去除过渡层。 对基板进行预烘烤处理。 进行外延生长工艺以在凹槽中生长嵌入的SiGe层。 去除一次性氮化硅间隔物。

公开(公告)号：US08183118B2

公开(公告)日：2012-05-22

申请号：US12868739

申请日：2010-08-26

Applicant: Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834

Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

Abstract translation: 本发明公开了一种制造MOS晶体管的方法。 提供其上具有栅极结构的基板。 氮化硅层沉积在栅极结构上。 然后执行干蚀刻工艺以在栅极结构的每个侧壁上限定氮化硅间隔物，并且在栅极结构的每一侧上的源极/漏极区域中形成凹陷。 沉积覆盖栅极结构和凹陷的过渡层。 执行预外延清洁处理以去除过渡层。 对基板进行预烘烤处理。 进行外延生长工艺以在凹槽中生长嵌入的SiGe层。 去除一次性氮化硅间隔物。

公开(公告)号：US20120202328A1

公开(公告)日：2012-08-09

申请号：US13450476

申请日：2012-04-19

Applicant: Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834

Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

公开(公告)号：US20120309171A1

公开(公告)日：2012-12-06

申请号：US13118473

申请日：2011-05-30

Applicant: Tsuo-Wen Lu ,  Wen-Yi Teng ,  Yu-Ren Wang ,  Gin-Chen Huang ,  Chien-Liang Lin ,  Shao-Wei Wang ,  Ying-Wei Yen ,  Ya-Chi Cheng ,  Shu-Yen Chan ,  Chan-Lon Yang

Inventor： Tsuo-Wen Lu ,  Wen-Yi Teng ,  Yu-Ren Wang ,  Gin-Chen Huang ,  Chien-Liang Lin ,  Shao-Wei Wang ,  Ying-Wei Yen ,  Ya-Chi Cheng ,  Shu-Yen Chan ,  Chan-Lon Yang

IPC: H01L21/20

CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底，其中衬底包括其上的栅极结构; 在所述衬底上形成膜叠层并覆盖所述栅极结构，其中所述膜堆叠至少包括氧化物层和氮化物层; 移除所述薄膜叠层的一部分以形成邻近所述栅极结构的两侧的凹槽和所述栅极结构侧壁上的一次性间隔物; 并用包含硅原子的材料填充凹部，以形成刻面材料层。

公开(公告)号：US20120329261A1

公开(公告)日：2012-12-27

申请号：US13164781

申请日：2011-06-21

Applicant: Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

Inventor： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

IPC: H01L21/782 ,  H01L21/28

CPC classification number: H01L29/7833 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract translation: 一种金属栅极的制造方法，包括提供具有至少形成有导电类型的半导体器件的衬底，在该半导体器件中形成栅极沟槽，形成具有导电类型的功函数金属层和对应于 栅极沟槽中的导电类型，并且执行离子注入以将功函数金属层的固有功函数调整到目标功函数。

公开(公告)号：US08536038B2

公开(公告)日：2013-09-17

申请号：US13164781

申请日：2011-06-21

Applicant: Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

Inventor： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

IPC: H01L21/3205 ,  H01L21/425

CPC classification number: H01L29/7833 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract translation: 一种金属栅极的制造方法，包括提供具有至少形成有导电类型的半导体器件的衬底，在该半导体器件中形成栅极沟槽，形成具有导电类型的功函数金属层和对应于 栅极沟槽中的导电类型，并且执行离子注入以将功函数金属层的固有功函数调整到目标功函数。

公开(公告)号：US20120326238A1

公开(公告)日：2012-12-27

申请号：US13167738

申请日：2011-06-24

Applicant: Chin-Cheng Chien ,  Tzung-Ying Lee ,  Tsuo-Wen Lu ,  Shu-Yen Chan ,  Jei-Ming Chen ,  Yu-Min Lin ,  Chun-Wei Hsu

Inventor： Chin-Cheng Chien ,  Tzung-Ying Lee ,  Tsuo-Wen Lu ,  Shu-Yen Chan ,  Jei-Ming Chen ,  Yu-Min Lin ,  Chun-Wei Hsu

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L29/7833 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供其上具有第一区域和第二区域的衬底; 在基板上形成高k电介质层，阻挡层和第一金属层; 去除第二区域的第一金属层; 形成多晶硅层以覆盖第一区域的第一金属层和第二区域的阻挡层; 图案化多晶硅层，第一金属层，势垒层和高k电介质层，以在第一区域和第二区域中形成第一栅极结构和第二栅极结构; 以及在所述衬底中邻近所述第一栅极结构和所述第二栅极结构的两侧形成源极/漏极。

公开(公告)号：US08674452B2

公开(公告)日：2014-03-18

申请号：US13167738

申请日：2011-06-24

Applicant: Chin-Cheng Chien ,  Tzung-Ying Lee ,  Tsuo-Wen Lu ,  Shu-Yen Chan ,  Jei-Ming Chen ,  Yu-Min Lin ,  Chun-Wei Hsu

Inventor： Chin-Cheng Chien ,  Tzung-Ying Lee ,  Tsuo-Wen Lu ,  Shu-Yen Chan ,  Jei-Ming Chen ,  Yu-Min Lin ,  Chun-Wei Hsu

IPC: H01L21/70

CPC classification number: H01L29/7833 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function metal layer; and a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the thickness of the second metal layer is lower than the thickness of the first metal layer.

Abstract translation: 半导体器件包括：具有第一区域和第二区域的衬底; 设置在所述第一区域上的第一栅极结构，其中所述第一栅极结构包括第一高k介电层，第一功函数金属层和设置在所述第一高k介电层与所述第一功函数之间的第一金属层 金属层 以及设置在所述第二区域上的第二栅极结构，其中所述第二栅极结构包括第二高k电介质层，第二功函数金属层和设置在所述第二高k电介质层和所述第二工件之间的第二金属层 功能金属层，其中所述第二金属层的厚度低于所述第一金属层的厚度。

公开(公告)号：US08580625B2

公开(公告)日：2013-11-12

申请号：US13188536

申请日：2011-07-22

Applicant: Tsuo-Wen Lu ,  Tzung-Ying Lee ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Yu-Min Lin ,  Chia-Lung Chang ,  Chin-Cheng Chien ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tzung-Ying Lee ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Yu-Min Lin ,  Chia-Lung Chang ,  Chin-Cheng Chien ,  Shu-Yen Chan

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.

Abstract translation: 提供一种制造MOS晶体管的方法。 基板在通过去除伪栅极并位于第一晶体管区域和第二晶体管区域中形成的第一开口和第二开口中的每一个中具有高k电介质层和势垒。 介电阻挡层形成在衬底上并填充到第一开口和第二开口中以覆盖阻挡层。 去除第一晶体管区域中的介电阻挡层的一部分。 形成第一功函数金属层。 去除第一功函数金属层和第二晶体管区域中的介电阻挡层的一部分。 形成第二功函数金属层。 该方法可以避免高k电介质层的损失，以保持栅极结构的可靠性，从而提高MOS晶体管的性能。

公开(公告)号：US20130020657A1

公开(公告)日：2013-01-24

申请号：US13188536

申请日：2011-07-22

Applicant: Tsuo-Wen LU ,  Tzung-Ying Lee ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Yu-Min Lin ,  Chia-Lung Chang ,  Chin-Cheng Chien ,  Shu-Yen Chan

Inventor： Tsuo-Wen LU ,  Tzung-Ying Lee ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Yu-Min Lin ,  Chia-Lung Chang ,  Chin-Cheng Chien ,  Shu-Yen Chan

IPC: H01L29/78 ,  H01L21/76 ,  H01L21/28

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.

Abstract translation: 提供一种制造MOS晶体管的方法。 基板在通过去除伪栅极并位于第一晶体管区域和第二晶体管区域中形成的第一开口和第二开口中的每一个中具有高k电介质层和势垒。 介电阻挡层形成在衬底上并填充到第一开口和第二开口中以覆盖阻挡层。 去除第一晶体管区域中的介电阻挡层的一部分。 形成第一功函数金属层。 去除第一功函数金属层和第二晶体管区域中的介电阻挡层的一部分。 形成第二功函数金属层。 该方法可以避免高k电介质层的损失，以保持栅极结构的可靠性，从而提高MOS晶体管的性能。