Invention Application
- Patent Title: METHOD FOR FABRICATING MOS TRANSISTOR
- Patent Title (中): 制造MOS晶体管的方法
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Application No.: US12868739Application Date: 2010-08-26
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Publication No.: US20120052644A1Publication Date: 2012-03-01
- Inventor: Tsuo-Wen Lu , Tsai-Fu Hsiao , Yu-Ren Wang , Shu-Yen Chan
- Applicant: Tsuo-Wen Lu , Tsai-Fu Hsiao , Yu-Ren Wang , Shu-Yen Chan
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.
Public/Granted literature
- US08183118B2 Method for fabricating MOS transistor Public/Granted day:2012-05-22
Information query
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