公开(公告)号：US20120052644A1

公开(公告)日：2012-03-01

申请号：US12868739

申请日：2010-08-26

Applicant: Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834

Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

Abstract translation: 本发明公开了一种制造MOS晶体管的方法。 提供其上具有栅极结构的基板。 氮化硅层沉积在栅极结构上。 然后执行干蚀刻工艺以在栅极结构的每个侧壁上限定氮化硅间隔物，并且在栅极结构的每一侧上的源极/漏极区域中形成凹陷。 沉积覆盖栅极结构和凹陷的过渡层。 执行预外延清洁处理以去除过渡层。 对基板进行预烘烤处理。 进行外延生长工艺以在凹槽中生长嵌入的SiGe层。 去除一次性氮化硅间隔物。

公开(公告)号：US20120068268A1

公开(公告)日：2012-03-22

申请号：US12888351

申请日：2010-09-22

Applicant: Tsai-Fu Hsiao ,  Tsuo-Wen Lu ,  Yu-Ren Wang

Inventor： Tsai-Fu Hsiao ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method of fabricating a transistor structure includes the step of providing a substrate having a gate thereon. Then, a first spacer is formed at two sides of the gate. After that, an LDD region is formed in the substrate at two sides of the gate. Later, a second spacer comprising a carbon-containing spacer and a sacrificing spacer is formed on the first spacer. Subsequently, a source/drain region is formed in the substrate at two sides of the gate. Finally, the sacrificing spacer is removed entirely, and part of the carbon-containing spacer is also removed. The remaining carbon-containing spacer has an L shape. The carbon-containing spacer has a first carbon concentration, and the sacrificing spacer has a second carbon concentration. The first carbon concentration is greater than the second carbon concentration.

Abstract translation: 制造晶体管结构的方法包括提供其上具有栅极的衬底的步骤。 然后，在栅极的两侧形成第一间隔物。 之后，在栅极两侧的基板上形成LDD区域。 之后，在第一间隔物上形成包含含碳间隔物和牺牲间隔物的第二间隔物。 随后，在栅极两侧的基板中形成源/漏区。 最后，完全除去牺牲间隔物，并且还除去部分含碳间隔物。 剩余的含碳隔离物具有L形。 含碳隔离物具有第一碳浓度，牺牲间隔物具有第二碳浓度。 第一个碳浓度大于第二个碳浓度。

公开(公告)号：US20120202328A1

公开(公告)日：2012-08-09

申请号：US13450476

申请日：2012-04-19

Applicant: Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834

Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

公开(公告)号：US08183118B2

公开(公告)日：2012-05-22

申请号：US12868739

申请日：2010-08-26

Applicant: Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834

Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

Abstract translation: 本发明公开了一种制造MOS晶体管的方法。 提供其上具有栅极结构的基板。 氮化硅层沉积在栅极结构上。 然后执行干蚀刻工艺以在栅极结构的每个侧壁上限定氮化硅间隔物，并且在栅极结构的每一侧上的源极/漏极区域中形成凹陷。 沉积覆盖栅极结构和凹陷的过渡层。 执行预外延清洁处理以去除过渡层。 对基板进行预烘烤处理。 进行外延生长工艺以在凹槽中生长嵌入的SiGe层。 去除一次性氮化硅间隔物。

公开(公告)号：US08921238B2

公开(公告)日：2014-12-30

申请号：US13235515

申请日：2011-09-19

Applicant: Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen

Inventor： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen

IPC: H01L21/31 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/3105 ,  H01L21/02148 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02192 ,  H01L21/02197 ,  H01L21/0228

Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.

Abstract translation: 一种用于处理高k电介质层的方法包括以下步骤。 提供半导体衬底，并且在其上形成高k电介质层。 高k电介质层具有结晶温度。 随后，进行第一退火处理，并且第一退火工艺的处理温度显着小于结晶温度。 进行第二退火处理，第二退火处理的工艺温度显着大于结晶温度。

公开(公告)号：US08536038B2

公开(公告)日：2013-09-17

申请号：US13164781

申请日：2011-06-21

Applicant: Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

Inventor： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

IPC: H01L21/3205 ,  H01L21/425

CPC classification number: H01L29/7833 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract translation: 一种金属栅极的制造方法，包括提供具有至少形成有导电类型的半导体器件的衬底，在该半导体器件中形成栅极沟槽，形成具有导电类型的功函数金属层和对应于 栅极沟槽中的导电类型，并且执行离子注入以将功函数金属层的固有功函数调整到目标功函数。

公开(公告)号：US20130072030A1

公开(公告)日：2013-03-21

申请号：US13235515

申请日：2011-09-19

Applicant: Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen

Inventor： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen

IPC: H01L21/314

CPC classification number: H01L21/3105 ,  H01L21/02148 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02192 ,  H01L21/02197 ,  H01L21/0228

Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.

Abstract translation: 一种用于处理高k电介质层的方法包括以下步骤。 提供半导体衬底，并且在其上形成高k电介质层。 高k电介质层具有结晶温度。 随后，进行第一退火处理，并且第一退火工艺的处理温度显着小于结晶温度。 进行第二退火处理，第二退火处理的工艺温度显着大于结晶温度。

公开(公告)号：US20120292720A1

公开(公告)日：2012-11-22

申请号：US13109999

申请日：2011-05-18

Applicant: Chih-Chung Chen ,  Yu-Ren Wang ,  Tsuo-Wen Lu ,  Wen-Yi Teng

Inventor： Chih-Chung Chen ,  Yu-Ren Wang ,  Tsuo-Wen Lu ,  Wen-Yi Teng

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: A metal gate structure includes a high dielectric constant (high-K) gate dielectric layer, a metal gate having at least a U-shaped work function metal layer positioned on the high-K gate dielectric layer, and a silicon carbonitride (SiCN) seal layer positioned on sidewalls of the high-K gate dielectric layer and of the metal gate.

Abstract translation: 金属栅极结构包括高介电常数（高K）栅极电介质层，至少具有位于高K栅极介电层上的U形功函数金属层的金属栅极和碳氮化硅（SiCN）密封 层位于高K栅极电介质层和金属栅极的侧壁上。

公开(公告)号：US20120329261A1

公开(公告)日：2012-12-27

申请号：US13164781

申请日：2011-06-21

Applicant: Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

Inventor： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

IPC: H01L21/782 ,  H01L21/28

CPC classification number: H01L29/7833 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract translation: 一种金属栅极的制造方法，包括提供具有至少形成有导电类型的半导体器件的衬底，在该半导体器件中形成栅极沟槽，形成具有导电类型的功函数金属层和对应于 栅极沟槽中的导电类型，并且执行离子注入以将功函数金属层的固有功函数调整到目标功函数。

公开(公告)号：US08697508B2

公开(公告)日：2014-04-15

申请号：US13451484

申请日：2012-04-19

Applicant: Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/3105 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. An oxide layer is formed and covers the gate structure and the substrate. A plasma process without oxygen is performed to densify the oxide layer. A material layer is formed and covers the oxide layer. The material layer and the oxide layer are etched to form a dual spacer.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成栅极结构。 形成氧化物层并覆盖栅极结构和衬底。 进行无氧的等离子体处理以致密化氧化物层。 形成材料层并覆盖氧化物层。 蚀刻材料层和氧化物层以形成双重间隔物。