公开(公告)号：US20080206942A1

公开(公告)日：2008-08-28

申请号：US11678627

申请日：2007-02-26

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

Abstract translation: 公开了制造应变硅晶体管的方法。 首先，提供半导体衬底，并且在半导体衬底上设置栅极结构和围绕栅极结构的间隔物。 然后在隔离物周围的半导体衬底中形成源极/漏极区域，并且执行第一快速热退火处理以激活源极/漏极区域内的掺杂剂。 执行蚀刻工艺以在栅极结构周围形成凹陷，并且执行选择性外延生长工艺以在凹部中形成外延层。 执行第二快速热退火处理以重新定义源/漏区域内的掺杂剂的分布并修复掺杂剂的损坏的键。

公开(公告)号：US08664073B2

公开(公告)日：2014-03-04

申请号：US12983894

申请日：2011-01-04

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/8238

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract translation: 公开了一种用于制造互补金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：（A）在衬底上形成第一栅极结构和第二栅极结构; （B）执行第一共注入工艺以限定与所述第一栅极结构的两侧相邻的所述衬底中的第一类型源极/漏极延伸区域深度分布; （C）在与第一栅极结构相邻的衬底中形成第一源极/漏极延伸区域; （D）执行第二共注入工艺以限定与所述第二栅极结构的两侧相邻的所述衬底中的第一袋区深度分布; （E）执行第一口袋注入工艺以形成与第二栅极结构的两侧相邻的第一袋区域。

公开(公告)号：US20120009745A1

公开(公告)日：2012-01-12

申请号：US12983894

申请日：2011-01-04

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/8238

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract translation: 公开了一种用于制造互补金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：（A）在衬底上形成第一栅极结构和第二栅极结构; （B）执行第一共注入工艺以限定与所述第一栅极结构的两侧相邻的所述衬底中的第一类型源极/漏极延伸区域深度分布; （C）在与第一栅极结构相邻的衬底中形成第一源极/漏极延伸区域; （D）执行第二共注入工艺以限定与所述第二栅极结构的两侧相邻的所述衬底中的第一袋区深度分布; （E）执行第一口袋注入工艺以形成与第二栅极结构的两侧相邻的第一袋区域。

公开(公告)号：US20090224328A1

公开(公告)日：2009-09-10

申请号：US12041668

申请日：2008-03-04

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzer-Min Shen

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzer-Min Shen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate defining an active area thereon, a shallow trench isolation on the substrate and directly surrounding the active area, a gate, a source and a drain on the active area and a hard mask on the border of the shallow trench isolation and the active area.

Abstract translation: 半导体器件包括限定其上的有源区的衬底，衬底上的浅沟槽隔离并且直接围绕有源区，有源区上的栅极，源极和漏极以及浅沟槽隔离边界上的硬掩模 和活动区域。

公开(公告)号：US20090186475A1

公开(公告)日：2009-07-23

申请号：US12017065

申请日：2008-01-21

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Yao-Chin Cheng ,  Chi-Sheng Tseng ,  Yu-Ming Lin ,  Shih-Jung Tu ,  Tzyy-Ming Cheng

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Yao-Chin Cheng ,  Chi-Sheng Tseng ,  Yu-Ming Lin ,  Shih-Jung Tu ,  Tzyy-Ming Cheng

IPC: H01L21/3205

CPC classification number: H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.

Abstract translation: 一种制造MOS晶体管的方法，其中使用三层光致抗蚀剂层来形成具有声音形状和小尺寸的图案化硬掩模层，并且使用图案化的硬掩模层来形成栅极。 此后，通过形成和限定盖层，通过在衬底中的蚀刻形成凹陷。 在凹槽中形成外延层之后去除图案化的硬掩模。 因此，可以避免导致接触桥的常规多晶块问题和STI氧化物损耗问题。

公开(公告)号：US20090166625A1

公开(公告)日：2009-07-02

申请号：US11966734

申请日：2007-12-28

Applicant: Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

Inventor： Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

IPC: H01L29/04 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract translation: 本发明提供一种形成金属氧化物半导体（MOS）器件的方法及其结构。 该方法至少包括通过第一选择性外延生长工艺形成硅锗层并通过第二选择性外延生长工艺在硅锗层上形成覆盖层的步骤。 因此，可以减轻离子注入引起的不良影响。

公开(公告)号：US20080242031A1

公开(公告)日：2008-10-02

申请号：US11692609

申请日：2007-03-28

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659

Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract translation: 制造p型沟道FET的方法包括在衬底上形成栅极。 然后，执行PAI离子注入工艺。 此外，进行袋注入工艺以形成袋区域。 此后，执行第一共注入工艺以限定源极/漏极延伸区域深度分布。 然后，形成p型源极/漏极延伸区域。 之后，执行第二共注入处理以限定源极/漏极区域深度分布。 此后，进行原位掺杂外延生长工艺以形成用作p型源/漏区的掺杂半导体化合物。

公开(公告)号：US20080237734A1

公开(公告)日：2008-10-02

申请号：US11693470

申请日：2007-03-29

Applicant: Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

Inventor： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor.

Abstract translation: 提供了包括基板，第一导电型MOS晶体管，第二导电型MOS晶体管，缓冲层，第一应力层和第二应力层的互补金属氧化物半导体（CMOS）晶体管。 衬底在其中具有限定第一有源区和第二有源区的器件隔离结构。 第一导电型MOS晶体管和第二导电型MOS晶体管分别设置在基板的第一有源区域和第二有源区域中。 第一导电型MOS晶体管的第一氮化物间隔物的厚度大于第二导电型MOS晶体管的第二氮化物间隔物的厚度。 缓冲层设置在第一导电型MOS晶体管上。 第一应力层设置在缓冲层上。 第二应力层设置在第二导电型MOS晶体管上。

公开(公告)号：US08222113B2

公开(公告)日：2012-07-17

申请号：US12469135

申请日：2009-05-20

Applicant: Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

Inventor： Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for forming a metal-oxide-semiconductor (MOS) device includes at least steps of forming a pair of trenches in a substrate at both sides of a gate structure, filling the trenches with a silicon germanium layer by a selective epitaxy growth process, forming a cap layer on the silicon germanium layer by a selective growth process, and forming a pair of source/drain regions by performing an ion implantation process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract translation: 形成金属氧化物半导体（MOS）器件的方法至少包括以下步骤：在栅极结构两侧的衬底中形成一对沟槽，通过选择性外延生长工艺用硅锗层填充沟槽， 通过选择性生长工艺在硅锗层上形成盖层，并通过进行离子注入工艺形成一对源/漏区。 因此，可以减轻离子注入引起的不良影响。

公开(公告)号：US20110104864A1

公开(公告)日：2011-05-05

申请号：US12985309

申请日：2011-01-05

Applicant: Li-Shian Jeng ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Wen-Han Hung ,  Kun-Hsien Lee ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Li-Shian Jeng ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Wen-Han Hung ,  Kun-Hsien Lee ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

Abstract translation: 提供了制造互补金属氧化物半导体（CMOS）器件的方法。 在衬底的第一区域中形成包括使用半导体化合物作为主要材料的源/漏区的第一导电型MOS晶体管。 在基板的第二区域中形成第二导电型MOS晶体管。 接下来，执行预非晶体注入（PAI）工艺以使第二导电型MOS晶体管的栅极导电层非晶化。 此后，在第二区域中的基板上形成应力转移方案（STS），以在栅极导电层中产生应力。 之后，进行快速热退火（RTA）处理以激活源极/漏极区域中的掺杂剂。 然后，STS被删除。