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    RESISTOR AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    RESISTOR AND MANUFACTURING METHOD THEREOF 有权
    电阻及其制造方法

    公开(公告)号：US20130049168A1

    公开(公告)日：2013-02-28

    申请号：US13215237

    申请日：2011-08-23

    申请人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

    发明人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

    IPC分类号： H01L21/8234 ,  H01L27/06

    CPC分类号： H01L28/20 ,  H01L27/0629

    摘要： A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

    摘要翻译： 一种用于形成与具有金属栅极的晶体管集成的电阻器的方法包括提供具有限定在其上的晶体管区域和电阻器区域的衬底，在晶体管区域中形成具有多晶硅虚拟栅极的晶体管，以及多晶硅主体部分，其中两个掺杂区域 在电阻器区域的两个相对端处，执行蚀刻工艺以去除多晶硅虚拟栅极以形成第一沟槽并去除掺杂区域的部分以形成两个第二沟槽，并且在第一沟槽中形成金属栅极以形成晶体管 在第二沟槽中分别具有金属栅极和金属结构以形成电阻器。

    Metal gate process
    5.
    发明授权
    Metal gate process 有权
    金属门工艺

    公开(公告)号：US08753968B2

    公开(公告)日：2014-06-17

    申请号：US13279355

    申请日：2011-10-24

    申请人： Kuang-Hung Huang ,  Po-Jui Liao ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang

    发明人： Kuang-Hung Huang ,  Po-Jui Liao ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang

    IPC分类号： H01L21/28

    CPC分类号： H01L21/823842 ,  H01L21/32139 ,  H01L29/4966 ,  H01L29/66545

    摘要： A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.

    摘要翻译： 金属浇口工艺包括以下步骤。 提供了衬底上的隔离层，隔离层具有第一凹部和第二凹部。 形成覆盖第一凹部和第二凹部的第一金属层。 材料填充在第一凹部中，但是露出第一凹部的顶部。 第一凹部的顶部和第二凹部中的第一金属层被同时移除。 材料被去除。 顺序地填充第一凹槽和第二凹槽中的第二金属层和金属栅极层。

    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 审中-公开
    具有金属门的半导体器件及其制造方法

    公开(公告)号：US20130099307A1

    公开(公告)日：2013-04-25

    申请号：US13278186

    申请日：2011-10-21

    申请人： Chi-Sheng Tseng ,  Jie-Ning Yang ,  Kuang-Hung Huang ,  Yao-Chang Wang ,  Po-Jui Liao ,  Shih-Chieh Hsu

    发明人： Chi-Sheng Tseng ,  Jie-Ning Yang ,  Kuang-Hung Huang ,  Yao-Chang Wang ,  Po-Jui Liao ,  Shih-Chieh Hsu

    IPC分类号： H01L29/78 ,  H01L21/762

    CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

    摘要： A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer in the first gate trench, forming a second work function metal layer in the first gate trench and the second gate trench, forming a first patterned mask layer exposing portions of the second work function metal layer in the first gate trench and the second gate trench, and performing an etching process to remove the exposed second work function metal layer.

    摘要翻译： 具有金属栅极的半导体器件的制造方法包括提供具有形成在其上的第一半导体器件和第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，并且所述第二半导体器件具有第二栅极沟槽，形成第一 在第一栅极沟槽中形成功函数金属层，在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层，形成暴露第一栅极沟槽中的第二功函数金属层的部分的第一图案化掩模层， 第二栅极沟槽，并且执行蚀刻工艺以去除暴露的第二功函数金属层。

    Resistor and manufacturing method thereof
    8.
    发明授权
    Resistor and manufacturing method thereof 有权
    电阻及其制造方法

    公开(公告)号：US08710593B2

    公开(公告)日：2014-04-29

    申请号：US13444851

    申请日：2012-04-12

    申请人： Chi-Sheng Tseng ,  Yao-Chang Wang ,  Jie-Ning Yang

    发明人： Chi-Sheng Tseng ,  Yao-Chang Wang ,  Jie-Ning Yang

    IPC分类号： H01L27/11

    CPC分类号： H01L28/24 ,  H01L27/0629

    摘要： A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.

    摘要翻译： 一种与具有金属栅极的晶体管集成的电阻器的制造方法，包括：提供具有晶体管的基板，过渡结构以及覆盖晶体管的过渡结构的介电层和在其上形成的过渡结构，在两个相对的多晶硅端部之间形成凹部 过渡结构，形成U形电阻调制层和填充凹槽的绝缘层，去除晶体管的虚拟栅极和过渡结构的多晶硅端部分别在晶体管中形成栅极沟槽和两个端子沟槽，以及 过渡结构，并且在栅极沟槽中形成金属栅极和端子沟槽中的导电端子。

    RESISTOR AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    RESISTOR AND MANUFACTURING METHOD THEREOF 有权
    电阻及其制造方法

    公开(公告)号：US20130270650A1

    公开(公告)日：2013-10-17

    申请号：US13444851

    申请日：2012-04-12

    申请人： Chi-Sheng Tseng ,  Yao-Chang Wang ,  Jie-Ning Yang

    发明人： Chi-Sheng Tseng ,  Yao-Chang Wang ,  Jie-Ning Yang

    IPC分类号： H01L27/13 ,  H01L21/02

    CPC分类号： H01L28/24 ,  H01L27/0629

    摘要： A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.

    摘要翻译： 一种与具有金属栅极的晶体管集成的电阻器的制造方法，包括：提供具有晶体管的基板，过渡结构以及覆盖晶体管的过渡结构的介电层和在其上形成的过渡结构，在两个相对的多晶硅端部之间形成凹部 过渡结构，形成U形电阻调制层和填充凹槽的绝缘层，去除晶体管的虚拟栅极和过渡结构的多晶硅端部分别在晶体管中形成栅极沟槽和两个端子沟槽，以及 过渡结构，并且在栅极沟槽中形成金属栅极和端子沟槽中的导电端子。

    Resistor and manufacturing method thereof
    10.
    发明授权
    Resistor and manufacturing method thereof 有权
    电阻及其制造方法

    公开(公告)号：US08981527B2

    公开(公告)日：2015-03-17

    申请号：US13215237

    申请日：2011-08-23

    申请人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

    发明人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

    IPC分类号： H01L21/8234 ,  H01L49/02 ,  H01L27/06

    CPC分类号： H01L28/20 ,  H01L27/0629

    摘要： A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

    摘要翻译： 一种用于形成与具有金属栅极的晶体管集成的电阻器的方法包括提供具有限定在其上的晶体管区域和电阻器区域的衬底，在晶体管区域中形成具有多晶硅虚拟栅极的晶体管，以及多晶硅主体部分，其中两个掺杂区域 在电阻器区域的两个相对端处，执行蚀刻工艺以去除多晶硅虚拟栅极以形成第一沟槽并去除掺杂区域的部分以形成两个第二沟槽，并且在第一沟槽中形成金属栅极以形成晶体管 在第二沟槽中分别具有金属栅极和金属结构以形成电阻器。