Invention Application
- Patent Title: METHOD OF FABRICATING SEMICONDUCTOR DEVICE
- Patent Title (中): 制造半导体器件的方法
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Application No.: US12985309Application Date: 2011-01-05
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Publication No.: US20110104864A1Publication Date: 2011-05-05
- Inventor: Li-Shian Jeng , Cheng-Tung Huang , Shyh-Fann Ting , Wen-Han Hung , Kun-Hsien Lee , Meng-Yi Wu , Tzyy-Ming Cheng
- Applicant: Li-Shian Jeng , Cheng-Tung Huang , Shyh-Fann Ting , Wen-Han Hung , Kun-Hsien Lee , Meng-Yi Wu , Tzyy-Ming Cheng
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.
Information query
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