公开(公告)号：US20130043512A1

公开(公告)日：2013-02-21

申请号：US13212834

申请日：2011-08-18

Applicant: Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

Inventor： Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/31 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/02274 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/324 ,  H01L29/66795

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

公开(公告)号：US08269289B2

公开(公告)日：2012-09-18

申请号：US13204137

申请日：2011-08-05

Applicant: Hongfa Luan

Inventor： Hongfa Luan

IPC: H01L21/02

CPC classification number: H01L21/022 ,  H01L21/02123 ,  H01L21/02175 ,  H01L21/02356 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.

Abstract translation: 公开了形成晶体管器件及其结构的方法。 在工件上形成第一电介质材料，并且在第一电介质材料上形成第二电介质材料。 工件被退火，使得第二电介质材料的一部分与第一电介质材料结合并形成第三电介质材料。 去除第二电介质材料，并在第三电介质材料上形成栅极材料。 栅极材料和第三介电材料被图案化以形成至少一个晶体管。

公开(公告)号：US08188551B2

公开(公告)日：2012-05-29

申请号：US11240698

申请日：2005-09-30

Applicant: Thomas Schulz ,  Hongfa Luan

Inventor： Thomas Schulz ,  Hongfa Luan

IPC: H01L29/76

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/66803 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Abstract translation: 公开了半导体器件及其制造方法。 互补的金属氧化物半导体（CMOS）器件包括PMOS晶体管，其具有包括第一参数的至少两个第一栅电极和具有包括第二参数的至少两个第二栅电极的NMOS晶体管，其中第二参数不同于第一参数 参数。 第一参数和第二参数可以包括PMOS和NMOS晶体管的栅电极材料的厚度或掺杂物分布。 至少两个第一栅电极和至少两个第二栅电极的第一和第二参数分别建立PMOS和NMOS晶体管的功函数。

公开(公告)号：US08017484B2

公开(公告)日：2011-09-13

申请号：US11635207

申请日：2006-12-07

Applicant: Hongfa Luan

Inventor： Hongfa Luan

IPC: H01L21/336

CPC classification number: H01L21/022 ,  H01L21/02123 ,  H01L21/02175 ,  H01L21/02356 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.

Abstract translation: 公开了形成晶体管器件及其结构的方法。 在工件上形成第一电介质材料，并且在第一电介质材料上形成第二电介质材料。 工件被退火，使得第二电介质材料的一部分与第一电介质材料结合并形成第三电介质材料。 去除第二电介质材料，并在第三电介质材料上形成栅极材料。 栅极材料和第三介电材料被图案化以形成至少一个晶体管。

公开(公告)号：US20060234433A1

公开(公告)日：2006-10-19

申请号：US11105880

申请日：2005-04-14

Applicant: Hongfa Luan ,  Prashant Majhi

Inventor： Hongfa Luan ,  Prashant Majhi

IPC: H01L21/8234

CPC classification number: H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/78

Abstract: Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (Si). The gate comprises a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

Abstract translation: 公开了晶体管及其制造方法。 提供工件，在工件上形成栅极电介质，并且通过将工件暴露于铪（Hf）的前体和硅（Si）的前体，在栅极电介质上形成栅极。 栅极包括Hf和Si的组合层。 栅极的Hf和Si的组合层建立了晶体管的阈值电压V SUB。 晶体管可以包括CMOS器件的单个NMOS晶体管或NMOS晶体管。

公开(公告)号：US08722473B2

公开(公告)日：2014-05-13

申请号：US13451183

申请日：2012-04-19

Applicant: Thomas Schulz ,  Hongfa Luan

Inventor： Thomas Schulz ,  Hongfa Luan

IPC: H01L21/336

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/66803 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Abstract translation: 公开了半导体器件及其制造方法。 互补的金属氧化物半导体（CMOS）器件包括PMOS晶体管，其具有包括第一参数的至少两个第一栅电极和具有包括第二参数的至少两个第二栅电极的NMOS晶体管，其中第二参数不同于第一参数 参数。 第一参数和第二参数可以包括PMOS和NMOS晶体管的栅电极材料的厚度或掺杂物分布。 至少两个第一栅电极和至少两个第二栅电极的第一和第二参数分别建立PMOS和NMOS晶体管的功函数。

公开(公告)号：US20120199909A1

公开(公告)日：2012-08-09

申请号：US13451183

申请日：2012-04-19

Applicant: Thomas Schulz ,  Hongfa Luan

Inventor： Thomas Schulz ,  Hongfa Luan

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/66803 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Abstract translation: 公开了半导体器件及其制造方法。 互补的金属氧化物半导体（CMOS）器件包括PMOS晶体管，其具有包括第一参数的至少两个第一栅电极和具有包括第二参数的至少两个第二栅电极的NMOS晶体管，其中第二参数不同于第一参数 参数。 第一参数和第二参数可以包括PMOS和NMOS晶体管的栅电极材料的厚度或掺杂物分布。 至少两个第一栅电极和至少两个第二栅电极的第一和第二参数分别建立PMOS和NMOS晶体管的功函数。

公开(公告)号：US20080050898A1

公开(公告)日：2008-02-28

申请号：US11508682

申请日：2006-08-23

Applicant: Hongfa Luan

Inventor： Hongfa Luan

IPC: H01L21/3205

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, disposing a gate dielectric material over the workpiece, and disposing a gate material over the gate dielectric material. Cl or F is introduced to the gate material, wherein introducing the Cl or F to the gate material affects a work function of the gate material. The gate material and the gate dielectric material are patterned, forming at least one transistor.

Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供工件，在工件上方设置栅极电介质材料，并在栅极电介质材料上方设置栅极材料。 Cl或F被引入栅极材料，其中将Cl或F引入栅极材料影响栅极材料的功函数。 图案化栅极材料和栅极电介质材料，形成至少一个晶体管。

公开(公告)号：US20070075384A1

公开(公告)日：2007-04-05

申请号：US11635207

申请日：2006-12-07

Applicant: Hongfa Luan

Inventor： Hongfa Luan

IPC: H01L29/94

CPC classification number: H01L21/022 ,  H01L21/02123 ,  H01L21/02175 ,  H01L21/02356 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.

Abstract translation: 公开了形成晶体管器件及其结构的方法。 在工件上形成第一电介质材料，并且在第一电介质材料上形成第二电介质材料。 工件被退火，使得第二电介质材料的一部分与第一电介质材料结合并形成第三电介质材料。 去除第二电介质材料，并在第三电介质材料上形成栅极材料。 栅极材料和第三介电材料被图案化以形成至少一个晶体管。

公开(公告)号：US20070052037A1

公开(公告)日：2007-03-08

申请号：US11434029

申请日：2006-05-15

Applicant: Hongfa Luan

Inventor： Hongfa Luan

IPC: H01L29/94

CPC classification number: H01L21/823842 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A semiconductor device includes a first transistor and a second transistor. The first transistor comprises at least one first gate electrode including a first metal layer. The second transistor comprises at least one second gate electrode including the first metal layer. The at least one first gate electrode or the at least one second gate electrode includes a second metal layer disposed over the first metal layer.

Abstract translation: 公开了半导体器件及其制造方法。 半导体器件包括第一晶体管和第二晶体管。 第一晶体管包括至少一个包括第一金属层的第一栅电极。 第二晶体管包括至少一个包括第一金属层的第二栅电极。 所述至少一个第一栅电极或所述至少一个第二栅电极包括设置在所述第一金属层上的第二金属层。