公开(公告)号：US08946829B2

公开(公告)日：2015-02-03

申请号：US13273527

申请日：2011-10-14

申请人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang ,  Chi-Wen Liu

发明人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang ,  Chi-Wen Liu

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/265 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/06 ,  H01L29/66818 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/7854

摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.

摘要翻译： 半导体装置包括具有成形翅片和规则翅片的鳍状场效应晶体管（FinFET）。 成形翅片的顶部可以比普通翅片的顶部更小，更大，更薄或更短。 成形翅片和规则翅片的底部是相同的。 FinFET可以仅具有一个或多个成形翅片，一个或多个规则翅片，或者成形翅片和规则翅片的混合物。 形成一个鳍片的半导体制造工艺包括形成一个鳍片的光刻开口，可选地掺杂鳍片的一部分，以及蚀刻鳍片的一部分。

公开(公告)号：US08853052B2

公开(公告)日：2014-10-07

申请号：US13204352

申请日：2011-08-05

申请人： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

发明人： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC分类号： H01L21/76 ,  H01L29/00 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055

摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.

摘要翻译： 公开了一种制造半导体器件的方法。 一种示例性方法包括提供衬底。 在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。 阻挡层和电介质层包括不同的材料。 该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。 该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。 此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

公开(公告)号：US08766379B2

公开(公告)日：2014-07-01

申请号：US13239804

申请日：2011-09-22

申请人： Kuan-Ting Liu ,  Liang-Gi Yao ,  Yasutoshi Okuno ,  Clement Hsingjen Wann

发明人： Kuan-Ting Liu ,  Liang-Gi Yao ,  Yasutoshi Okuno ,  Clement Hsingjen Wann

IPC分类号： H01L21/02

CPC分类号： H01L21/823842 ,  H01L21/28008 ,  H01L21/28079 ,  H01L21/28088 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.

摘要翻译： 公开了一种多层扫气金属栅叠层及其制造方法。 在一个示例中，设置在半导体衬底上的栅极堆叠包括设置在半导体衬底上的界面电介质层，设置在界面电介质层上的高k电介质层，设置在高k电介质层上的第一导电层，以及 设置在所述第一导电层上的第二导电层。 第一导电层包括设置在高k电介质层上的第一金属层，设置在第一金属层上的第二金属层和设置在第二金属层上的第三金属层。 第一金属层包括从界面电介质层清除氧杂质的材料，第二金属层包括从第三金属层吸附氧杂质并防止氧杂质扩散到第一金属层中的材料。

公开(公告)号：US08716765B2

公开(公告)日：2014-05-06

申请号：US13428972

申请日：2012-03-23

申请人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/94

CPC分类号： H01L29/66545 ,  H01L21/02609 ,  H01L21/28506 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact structure for a semiconductor device includes a substrate comprising a major surface and a cavity. A bottom surface of the cavity is lower than the major surface. The contact structure also includes a strained material in the cavity, and a lattice constant of the strained material is different from lattice constant of the substrate. The contact structure also includes a first metal layer over the strained material, a dielectric layer over the first metal layer, and a second metal layer over the dielectric layer. The dielectric layer has a thickness ranging from 1 nm to 10 nm.

摘要翻译： 用于半导体器件的接触结构包括包括主表面和腔的衬底。 空腔的底面低于主面。 接触结构还包括空腔中的应变材料，并且应变材料的晶格常数不同于衬底的晶格常数。 接触结构还包括应变材料上的第一金属层，第一金属层上的电介质层和介电层上的第二金属层。 电介质层的厚度范围为1nm至10nm。

公开(公告)号：US20140048888A1

公开(公告)日：2014-02-20

申请号：US13588860

申请日：2012-08-17

申请人： Chung-Hsien Chen ,  Ting-Chu Ko ,  Chih-Hao Chang ,  Chih-Sheng Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann

发明人： Chung-Hsien Chen ,  Ting-Chu Ko ,  Chih-Hao Chang ,  Chih-Sheng Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L21/02664 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.

公开(公告)号：US20130320452A1

公开(公告)日：2013-12-05

申请号：US13486343

申请日：2012-06-01

申请人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

发明人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。 半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。 半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。 常见的接触特征是自对准接触。

公开(公告)号：US20130234203A1

公开(公告)日：2013-09-12

申请号：US13415710

申请日：2012-03-08

申请人： Ji-Yin Tsai ,  Yao-Tsung Huang ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Ji-Yin Tsai ,  Yao-Tsung Huang ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0886 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在工件中形成沟道区域，以及在沟道区域附近形成源极或漏极区域。 源极或漏极区包括包含SiP，SiA或硅化物的接触电阻降低材料层。 源极或漏极区域还包括包含SiCP或SiCAs的沟道应力材料层。

公开(公告)号：US20130221491A1

公开(公告)日：2013-08-29

申请号：US13403630

申请日：2012-02-23

申请人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yuan-Fu Shao ,  Wen-Huei Guo ,  Tung Ying Lee

发明人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yuan-Fu Shao ,  Wen-Huei Guo ,  Tung Ying Lee

IPC分类号： H01L29/02 ,  H01L21/336

CPC分类号： H01L29/42368 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/02 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/7856

摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.

摘要翻译： 半导体装置包括具有受控制的翅片高度的鳍状场效应晶体管（FinFET）。 该装置包括高翅片密度区域和低翅片密度区域。 每个翅片密度区域包括翅片和翅片之间的电介质材料。 电介质材料包括用于不同翅片密度区域的不同掺杂剂浓度，并且是与沉积物相同的材料。

公开(公告)号：US20130119405A1

公开(公告)日：2013-05-16

申请号：US13295178

申请日：2011-11-14

申请人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/772

CPC分类号： H01L29/0847 ,  H01L21/76224 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括半导体衬底。 半导体器件包括设置在衬底上的栅极。 基板具有凹部。 半导体器件包括沿着凹部涂覆的沟槽衬垫。 沟槽衬垫包含半导体晶体材料。 沟槽衬垫直接邻接源极/漏极应力器件。 半导体器件还包括设置在沟槽衬垫上并填充凹槽的电介质沟槽部件。 半导体器件包括设置在衬底中的源极/漏极应力器件。 源极/漏极应力器件设置在栅极和沟槽衬垫之间。

公开(公告)号：US08375349B2

公开(公告)日：2013-02-12

申请号：US12828591

申请日：2010-07-01

申请人： Clement Hsingjen Wann

发明人： Clement Hsingjen Wann

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5068

摘要： A method for constant power density scaling in MOSFETs is provided. A method for manufacturing an integrated circuit includes computing fixed scaling factors for a first fabrication process based on a second fabrication process, computing settable scaling factors for the integrated circuit to be fabricated using the first fabrication process, determining parameters of the integrated circuit based on the settable scaling factors, and manufacturing the integrated circuit using the determined parameters. The first fabrication process creates devices having a smaller device dimension than the second fabrication process and the settable scaling factors are set based on the fixed scaling factors.