公开(公告)号：US08769446B2

公开(公告)日：2014-07-01

申请号：US13227809

申请日：2011-09-08

申请人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin ,  Ming-Feng Shieh

发明人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin ,  Ming-Feng Shieh

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G03F1/00 ,  G06F17/5068 ,  H01L29/66795

摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. A plurality of elongate mandrels is defined in a plurality of active regions. Where adjacent active regions are partially-parallel and within a specified minimum spacing, connective elements are added to a portion of the space between the adjacent active regions to connect the mandrel ends from one active region to another active region.

摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 多个细长心轴被限定在多个有源区域中。 在相邻有源区域部分平行并且在规定的最小间隔内，连接元件被添加到相邻有源区域之间的空间的一部分，以将心轴端部从一个有源区域连接到另一个有源区域。

公开(公告)号：US08726220B2

公开(公告)日：2014-05-13

申请号：US13416742

申请日：2012-03-09

申请人： Yi-Tang Lin ,  Cheok-Kei Lei ,  Shu-Yu Chen ,  Yu-Ning Chang ,  Hsiao-Hui Chen ,  Chih-Sheng Chang ,  Chien-Wen Chen ,  Clement Hsingjen Wann

发明人： Yi-Tang Lin ,  Cheok-Kei Lei ,  Shu-Yu Chen ,  Yu-Ning Chang ,  Hsiao-Hui Chen ,  Chih-Sheng Chang ,  Chien-Wen Chen ,  Clement Hsingjen Wann

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5068 ,  H01L21/823821 ,  H01L27/0207

摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局，并以相符的方式生成对应的FinFET结构。 然后优化所得的FinFET结构。 在验证并输出FinFET布局之前，可能会产生虚拟图案和新的金属层。

公开(公告)号：US20130175638A1

公开(公告)日：2013-07-11

申请号：US13346411

申请日：2012-01-09

申请人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

发明人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.

摘要翻译： 一种方法包括在第一半导体鳍上形成包括栅电极的栅叠层。 栅极电极包括在第一半导体鳍片的中间部分上并对准的部分。 第二半导体鳍片位于栅电极的一侧，并且不延伸至栅电极下方。 第一和第二半导体散热片彼此间隔开并平行。 蚀刻第一半导体鳍片和第二半导体鳍片的端部。 进行外延以形成外延区域，其包括延伸到由第一半导体鳍片的蚀刻的第一端部分留下的第一空间的第一部分和延伸到由蚀刻的第二半导体鳍留下的第二空间的第二部分。 在外延区域形成第一源极/漏极区域。

公开(公告)号：US20130166248A1

公开(公告)日：2013-06-27

申请号：US13336306

申请日：2011-12-23

申请人： Chih-Sheng Chang ,  Chia-Cheng Ho ,  Yi-Tang Lin

发明人： Chih-Sheng Chang ,  Chia-Cheng Ho ,  Yi-Tang Lin

IPC分类号： G06F15/00 ,  H01L21/66

CPC分类号： H01L22/12 ,  G01B7/06 ,  H01L21/823431 ,  H01L22/34

摘要： A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

摘要翻译： 用于估计其它半导体器件中的外延生长的半导体材料的高度的方法和装置。 该方法包括在第一半导体器件上外延生长半导体材料的第一，第二和第三部分，测量半导体材料的第三部分的高度和半导体材料的第一或第二部分的高度，测量第一饱和电流通过 半导体材料的第一和第二部分，测量通过半导体材料的第一和第三部分的第二饱和电流，以及制备相对于半导体材料的第一或第二部分的高度和第二饱和度的第一饱和电流的模型 电流相对于半导体材料的第一和第三部分的高度的平均值。 该模型用于估计其它半导体器件中外延生长的半导体材料的高度。

公开(公告)号：US20130019219A1

公开(公告)日：2013-01-17

申请号：US13182338

申请日：2011-07-13

申请人： Shu-Yu Chen ,  Yi-Tang Lin ,  Cheok-Kei Lei ,  Hsiao-Hui Chen ,  Yu-Ning Chang ,  Hsingjen Wann ,  Chih-Sheng Chang ,  Chien-Wen Chen

发明人： Shu-Yu Chen ,  Yi-Tang Lin ,  Cheok-Kei Lei ,  Hsiao-Hui Chen ,  Yu-Ning Chang ,  Hsingjen Wann ,  Chih-Sheng Chang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an original layout and a revised layout includes, for each pattern of the original layout, determining a pattern of the revised layout that corresponds to the pattern of the original layout; and assigning the corresponding pattern of the revised layout to a temporary instance, the temporary instance corresponding to an instance of the pattern of the original layout and citing to a temporary cell. The method further includes creating a temporary reconstructed layout from the temporary instances; and producing the reconstructed layout from the temporary reconstructed layout, wherein a hierarchy of the reconstructed layout is similar to a hierarchy of the original layout.

摘要翻译： 描述了从扁平化布局进行层次重建的系统和方法。 在一个实施例中，从原始布局和经修改的布局生成用于集成电路设计的重建布局的方法包括：对于原始布局的每个图案，确定对应于原始布局的图案的修改布局的图案 ; 以及将修改的布局的相应模式分配给临时实例，所述临时实例对应于原始布局的模式的实例并引用临时小区。 该方法还包括从临时实例创建临时重建的布局; 以及从所述临时重建布局生成重建的布局，其中所述重构布局的层级类似于所述原始布局的层级。

公开(公告)号：US20120278776A1

公开(公告)日：2012-11-01

申请号：US13416642

申请日：2012-03-09

申请人： Cheok-Kei LEI ,  Yi-Tang LIN ,  Hsiao-Hui CHEN ,  Yu-Ning CHANG ,  Shu-Yu CHEN ,  Chien-Wen CHEN ,  Chih-Sheng CHANG ,  Clement Hsingjen WANN

发明人： Cheok-Kei LEI ,  Yi-Tang LIN ,  Hsiao-Hui CHEN ,  Yu-Ning CHANG ,  Shu-Yu CHEN ,  Chien-Wen CHEN ,  Chih-Sheng CHANG ,  Clement Hsingjen WANN

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L21/823821

摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.

摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局并生成相应的FinFET结构。

公开(公告)号：US20120126325A1

公开(公告)日：2012-05-24

申请号：US12952376

申请日：2010-11-23

申请人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin

发明人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/823431 ,  H01L21/845

摘要： A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.

摘要翻译： 一种方法包括在半导体衬底的表面上生长多个平行心轴，每个心轴具有至少两个横向相对的侧壁和预定宽度。 该方法还包括在心轴的侧壁上形成第一类型的间隔物，其中两个相邻心轴之间的第一类型的间隔物被间隙分开。 调整预定的心轴宽度以封闭相邻的第一类型间隔件之间的间隙，以形成第二类型的间隔件。 去除心轴以形成第一类型的间隔件的第一类型的翅片，并且在两个相邻的心轴之间从间隔件形成第二类型的翅片。 翅片的第二种类型比第一种翅片宽。

公开(公告)号：US08946829B2

公开(公告)日：2015-02-03

申请号：US13273527

申请日：2011-10-14

申请人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang ,  Chi-Wen Liu

发明人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang ,  Chi-Wen Liu

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/265 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/06 ,  H01L29/66818 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/7854

摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.

摘要翻译： 半导体装置包括具有成形翅片和规则翅片的鳍状场效应晶体管（FinFET）。 成形翅片的顶部可以比普通翅片的顶部更小，更大，更薄或更短。 成形翅片和规则翅片的底部是相同的。 FinFET可以仅具有一个或多个成形翅片，一个或多个规则翅片，或者成形翅片和规则翅片的混合物。 形成一个鳍片的半导体制造工艺包括形成一个鳍片的光刻开口，可选地掺杂鳍片的一部分，以及蚀刻鳍片的一部分。

公开(公告)号：US08906710B2

公开(公告)日：2014-12-09

申请号：US13336306

申请日：2011-12-23

申请人： Chih-Sheng Chang ,  Chia-Cheng Ho ,  Yi-Tang Lin

发明人： Chih-Sheng Chang ,  Chia-Cheng Ho ,  Yi-Tang Lin

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  G01B7/06 ,  H01L21/823431 ,  H01L22/34

摘要： A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

摘要翻译： 用于估计其它半导体器件中的外延生长的半导体材料的高度的方法和装置。 该方法包括在第一半导体器件上外延生长半导体材料的第一，第二和第三部分，测量半导体材料的第三部分的高度和半导体材料的第一或第二部分的高度，测量第一饱和电流通过 半导体材料的第一和第二部分，测量通过半导体材料的第一和第三部分的第二饱和电流，以及制备相对于半导体材料的第一或第二部分的高度和第二饱和度的第一饱和电流的模型 电流相对于半导体材料的第一和第三部分的高度的平均值。 该模型用于估计其它半导体器件中外延生长的半导体材料的高度。

公开(公告)号：US08609499B2

公开(公告)日：2013-12-17

申请号：US13346411

申请日：2012-01-09

申请人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

发明人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.