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公开(公告)号：US20240306516A1
公开(公告)日：2024-09-12
申请号：US18665145
申请日：2024-05-15
发明人： Jijun SUN
摘要： Aspects of the present disclosure are directed to magnetoresistive stacks including regions having increased height-to-diameter ratios. Exemplary magnetoresistive stacks (for example, used in a magnetic tunnel junction (MTJ) magnetoresistive device) of the present disclosure include one or more multilayer synthetic antiferromagnetic structures (SAFs) or synthetic ferromagnetic structures (SyFs) in order to promote stability of the SAF or SyF, e.g., for smaller-sized MTJs.
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公开(公告)号：US11944015B2
公开(公告)日：2024-03-26
申请号：US17659506
申请日：2022-04-18
发明人： Han-Jong Chia
CPC分类号： H10N50/80 , G11C11/161 , G11C11/1675 , H01F10/3272 , H01F10/3286 , H01F10/329 , H10B61/22 , H10N50/85
摘要： Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT segments injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction in order to improve the efficiency of the switching current applied to the magnetoresistive device.
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公开(公告)号：US20230403943A1
公开(公告)日：2023-12-14
申请号：US18456293
申请日：2023-08-25
摘要： A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
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公开(公告)号：US20230403011A1
公开(公告)日：2023-12-14
申请号：US18329793
申请日：2023-06-06
发明人： Syed M. ALAM , Sanjeev AGGARWAL
IPC分类号： H03K19/1776 , H10B61/00 , H01L23/498 , H10N50/10 , H01L23/48
CPC分类号： H03K19/1776 , H10B61/00 , H01L23/49816 , H10N50/10 , H01L23/481
摘要： A memory device includes a printed circuit board, a magnetoresistive random-access memory (MRAM) device coupled to the printed circuit board, a controller or control circuitry, wherein the controller or control circuitry is integrated into, embedded in, or otherwise incorporated into the MRAM device, and a field programmable gate array (FPGA) coupled to the printed circuit board and in communication with the controller or control circuitry.
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公开(公告)号：US11758823B2
公开(公告)日：2023-09-12
申请号：US16188934
申请日：2018-11-13
发明人： Jijun Sun , Jon Slaughter , Renu Whig
摘要： A magnetically free region of magnetoresistive device includes at least a first ferromagnetic region and a second ferromagnetic region separated by a non-magnetic insertion region. At least one of the first ferromagnetic region and the second ferromagnetic region may include at least a boron-rich ferromagnetic layer positioned proximate a boron-free ferromagnetic layer.
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公开(公告)号：US20230267982A1
公开(公告)日：2023-08-24
申请号：US17847265
申请日：2022-06-23
发明人： Syed M. ALAM
IPC分类号： G11C11/16 , H01L23/525 , H01L43/08 , H01L43/02
CPC分类号： G11C11/1695 , G11C11/1673 , G11C11/1675 , G11C11/1657 , H01L23/5252 , H01L43/08 , H01L43/02
摘要： The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.
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公开(公告)号：US11678584B2
公开(公告)日：2023-06-13
申请号：US17245882
申请日：2021-04-30
发明人： Renu Whig , Phillip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
IPC分类号： H10N50/01 , B82Y25/00 , G01R33/00 , G01R33/09 , H10B61/00 , H10N59/00 , H10N50/10 , H10N50/80
CPC分类号： H10N50/01 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H10B61/00 , H10N50/10 , H10N50/80 , H10N59/00
摘要： A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
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公开(公告)号：US11626146B1
公开(公告)日：2023-04-11
申请号：US17455292
申请日：2021-11-17
发明人： Syed M. Alam
摘要： The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.
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公开(公告)号：USRE49404E1
公开(公告)日：2023-01-31
申请号：US15470997
申请日：2017-03-28
发明人： Phillip Mather , Jon Slaughter , Nicholas Rizzo
摘要： Three bridge circuits (101, 111, 121), each include magnetoresistive sensors coupled as a Wheatstone bridge (100) to sense a magnetic field (160) in three orthogonal directions (110, 120, 130) that are set with a single pinning material deposition and bulk wafer setting procedure. One of the three bridge circuits (121) includes a first magnetoresistive sensor (141) comprising a first sensing element (122) disposed on a pinned layer (126), the first sensing element (122) having first and second edges and first and second sides, and a first flux guide (132) disposed non-parallel to the first side of the substrate and having an end that is proximate to the first edge and on the first side of the first sensing element (122). An optional second flux guide (136) may be disposed non-parallel to the first side of the substrate and having an end that is proximate to the second edge and the second side of the first sensing element (122).
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公开(公告)号：US11502247B2
公开(公告)日：2022-11-15
申请号：US17134683
申请日：2020-12-28
发明人： Sanjeev Aggarwal , Shimon , Kerry Joseph Nagel
摘要： A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.
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