公开(公告)号：US08794498B2

公开(公告)日：2014-08-05

申请号：US13181614

申请日：2011-07-13

Applicant: Yuji Kimura ,  Hiroki Horiguchi

Inventor： Yuji Kimura ,  Hiroki Horiguchi

IPC: B23K31/02 ,  H01L21/44 ,  H01L21/441 ,  B81C3/00 ,  B81C1/00 ,  H01L23/00

CPC classification number: B81C3/001 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/036 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/166 ,  H01L2924/3025 ,  Y10T428/31678 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a method for producing an electronic component device, a heat bonding step is performed in a state in which low melting point metal layers including low melting point metals including, for example, Sn as the main component, are arranged to sandwich, in the thickness direction, a high melting point metal layer including a high melting point metal including, for example, Cu as the main component, which is the same or substantially the same as high melting point metals defining first and second conductor films to be bonded. In order to generate an intermetallic compound of the high melting point metal and the low melting point metal, the distance in which the high melting point metal is to be diffused in each of the low melting point metal layers is reduced. Thus, the time required for the diffusion is reduced, and the time required for the bonding is reduced.

Abstract translation: 在电子部件装置的制造方法中，以包含例如以Sn为主要成分的低熔点金属的低熔点金属层配置成将厚度夹层的状态进行热粘合工序 方向，包括例如以Cu为主要成分的高熔点金属的高熔点金属层，其与限定要结合的第一和第二导体膜的高熔点金属相同或基本相同。 为了产生高熔点金属和低熔点金属的金属间化合物，降低了在每个低熔点金属层中高熔点金属扩散的距离。 因此，扩散所需的时间减少，并且键合所需的时间减少。

公开(公告)号：US20140199804A1

公开(公告)日：2014-07-17

申请号：US14215296

申请日：2014-03-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Jeng-Shyan Lin ,  Cheng-Ying Ho

IPC: H01L31/02 ,  H01L31/0232 ,  H01L23/00

CPC classification number: H01L31/02005 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14698 ,  H01L31/02327 ,  H01L2224/0345 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor device includes providing a device substrate having a front side and a back side corresponding to a front side and a back side of the semiconductor device, forming, on the front side of the device substrate, a metal feature, forming, on the back side of the device substrate, an insulating layer, forming, on the back side of the semiconductor device, a trench exposing the metal feature, forming a bonding pad in the trench in electrical communication with the metal feature, and forming, on the insulating layer, a metal shield, in which the metal shield and the bonding pad have different thicknesses relative to each other.

Abstract translation: 一种制造半导体器件的方法包括提供具有与半导体器件的前侧和后侧对应的前侧和后侧的器件基板，在器件基板的正面上形成金属特征，形成 在所述器件基板的背侧，形成绝缘层，在所述半导体器件的背侧形成暴露所述金属特征的沟槽，在所述沟槽中形成与所述金属特征电连通的接合焊盘， 在绝缘层上的金属屏蔽层，金属屏蔽层和焊盘相对于彼此具有不同的厚度。

公开(公告)号：US08772920B2

公开(公告)日：2014-07-08

申请号：US13182220

申请日：2011-07-13

Applicant: Hiren D. Thacker ,  John E. Cunningham ,  Ivan Shubin ,  Ashok V. Krishnamoorthy

Inventor： Hiren D. Thacker ,  John E. Cunningham ,  Ivan Shubin ,  Ashok V. Krishnamoorthy

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/481 ,  H01L2224/48227 ,  H01L2224/73103 ,  H01L2224/81138 ,  H01L2224/81899 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/01327 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

Abstract translation: 在芯片封装中，半导体管芯或芯片（被称为“板堆叠”）的垂直堆叠中的半导体管芯通过机械耦合到相邻半导体管芯的表面下方的负特性的正特征对准。 此外，芯片封装包括与板堆叠大致成直角的插入板，其沿着板堆的边缘电耦合到半导体管芯。 特别地，靠近插入板的表面（沿着板堆叠的堆叠方向）的电焊盘通过中间导电材料（例如焊料球）电耦合到靠近半导体管芯的边缘的焊盘， 弹簧连接器。 注意，芯片封装可以促进半导体管芯和插入板之间的信号的高带宽通信。

公开(公告)号：US08753983B2

公开(公告)日：2014-06-17

申请号：US12683961

申请日：2010-01-07

Applicant: Jin-Wook Jang ,  Lalgudi M. Mahalingam ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

Inventor： Jin-Wook Jang ,  Lalgudi M. Mahalingam ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L23/373 ,  H01L23/057 ,  H01L23/3731 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0489 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.

Abstract translation: 一种方法包括提供含硅模头并且在散热器的第一表面上提供具有钯层的散热器。 第一金层位于管芯的第一表面或钯层之一上。 所述含硅芯片与所述散热器接合，其中，所述接合包括将所述含硅芯片与所述散热器接合，使得所述第一金层和所述钯层位于所述含硅模具的所述第一表面和所述第一表面之间 并且加热所述第一金层和所述钯层以在所述含硅芯片的所述第一表面和所述散热器的所述第一表面之间形成管芯附着层，所述管芯附着层包括金界面层，所述金界面层具有 多个金属间化合物沉淀物，多个金属间析出物中的每一个包括钯，金和硅。

公开(公告)号：US20140159235A1

公开(公告)日：2014-06-12

申请号：US14073144

申请日：2013-11-06

Applicant: FUJITSU LIMITED

Inventor： Muneyuki Odaira

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11614 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/00

Abstract: An electronic component includes an electrode portion and a solder portion formed on the electrode portion. In the electronic component, the electrode portion includes a first conductive portion and a second conductive portion each having different diffusion coefficient with respect to a component of the solder portion on a top surface of the electrode portion, and the solder portion is formed on the first conductive portion and the second conductive portion.

Abstract translation: 电子部件包括在电极部上形成的电极部和焊料部。 在电子部件中，电极部包括第一导电部和第二导电部，所述第一导电部和第二导电部相对于电极部的顶面上的焊料部的成分具有不同的扩散系数，焊料部形成在第一导电部 导电部分和第二导电部分。

公开(公告)号：US20140151881A1

公开(公告)日：2014-06-05

申请号：US14177527

申请日：2014-02-11

Applicant: Tessera, Inc.

Inventor： Andrey Grinman ,  David Ovrutsky ,  Charles Rosenstein ,  Vage Oganesian

IPC: H01L23/498

CPC classification number: H01L23/3128 ,  H01L23/29 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/556 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16148 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract translation: 一种芯片尺寸的晶片级封装器件，其包括半导体晶片的一部分，其包括器件，至少一个包含硅并且形成在器件上的封装层，形成在所述至少一个封装层的表面上的第一球栅阵列;以及 电连接到所述装置，以及形成在所述半导体晶片的所述部分的表面上并且电连接到所述装置的第二球栅阵列。

公开(公告)号：US08733620B2

公开(公告)日：2014-05-27

申请号：US11297722

申请日：2005-12-08

Applicant: Mukul Renavikar ,  Susheel G. Jadhav

Inventor： Mukul Renavikar ,  Susheel G. Jadhav

IPC: B23K1/19

CPC classification number: H01L23/3735 ,  B23K1/0008 ,  B23K1/20 ,  B23K2103/12 ,  H01L21/4882 ,  H01L23/3736 ,  H01L2224/04026 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/00

Abstract: A solder is deposited on a heat sink. The solder is first reflowed at a first temperature that is below about 120° C. The solder is second heat aged at a temperature that causes the first reflowed solder to have an increased second reflow temperature. The heat aging process results in less compressive stress in a die that uses the solder as a thermal interface material. The solder can have a composition that reflows and adheres to the die and the heat sink without the use of organic fluxes.

Abstract translation: 焊料沉积在散热片上。 首先在小于约120℃的第一温度下回流焊料。在使第一回流焊料具有增加的第二回流温度的温度下，焊料被第二次热老化。 热老化过程导致使用焊料作为热界面材料的管芯中较小的压应力。 焊料可以具有在不使用有机焊剂的情况下回流并粘附到模具和散热器的组合物。

公开(公告)号：US20140138821A1

公开(公告)日：2014-05-22

申请号：US14164908

申请日：2014-01-27

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Hueng Jae OH ,  Tae Joon CHUNG ,  Dong Gyu LEE ,  Seon Jae MUN ,  Jin Won CHOI

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12042 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/1025 ,  Y02P70/613 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: Disclosed herein is substrate for flip chip bonding, in which a base solder layer is formed between a pad and a metal post, thereby increasing impact resistance and mounting reliability. A method of fabricating the substrate for flip chip bonding is also provided.

Abstract translation: 这里公开了用于倒装芯片接合的基板，其中在焊盘和金属柱之间形成基底焊料层，从而提高耐冲击性和安装可靠性。 还提供了一种制造用于倒装芯片接合的基板的方法。

公开(公告)号：US20140134798A1

公开(公告)日：2014-05-15

申请号：US14158131

申请日：2014-01-17

Applicant: Won-keun KIM ,  Hyun-jung SONG ,  Eun-young CHOI ,  Hye-young JANG

Inventor： Won-keun KIM ,  Hyun-jung SONG ,  Eun-young CHOI ,  Hye-young JANG

IPC: H01L25/00 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes.

Abstract translation: 一种半导体封装，包括：内部封装，其包括至少一个用内部密封件密封的半导体芯片;外部基板，其上安装有内部封装;以及外部密封件封装内部封装。 还提供了一种制造半导体封装的方法，包括形成包括至少一个用内部密封件密封的半导体芯片的内部封装，将内部封装安装在外部基板上，并用外部密封件密封内部封装。 内部密封件和外部密封件具有不同的杨氏模量，例如，内部密封件的杨氏模量小于外部密封件的杨氏模量。 因此，半导体封装不易翘曲，并且可以在随后的半导体封装工艺中相对容易地处理。

公开(公告)号：US20140131891A1

公开(公告)日：2014-05-15

申请号：US14157093

申请日：2014-01-16

Applicant: Lapis Semiconductor Co., Ltd.

Inventor： Masamichi Ishihara

IPC: H01L23/48 ,  H01L25/04

CPC classification number: H01L23/481 ,  H01L23/3157 ,  H01L23/48 ,  H01L23/488 ,  H01L23/49838 ,  H01L24/13 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0657 ,  H01L29/78 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.

Abstract translation: 薄堆叠半导体器件具有多个电路，其以指定图案依次层叠并形成以形成多层布线部。 在形成多层布线部的阶段，在半导体基板上形成填充电极，使得表面被绝缘膜覆盖，在多层布线部的特定布线上形成柱状电极，形成第一绝缘层 在半导体衬底的一个表面上，将第一绝缘层的表面去除特定厚度以暴露后电极，并且研磨半导体衬底的另一个表面以露出填充电极并形成通孔型电极 。 如果形成在半导体衬底的一个表面上同时暴露通孔型电极的前端的第二绝缘层，并且在两个电极上形成凸块电极。