公开(公告)号：US09972370B2

公开(公告)日：2018-05-15

申请号：US15045941

申请日：2016-02-17

Applicant: SK hynix Inc.

Inventor： Nam Jae Lee

IPC: G11C11/34 ,  G11C7/12 ,  G11C5/06 ,  G11C7/10 ,  G11C7/18 ,  H01L27/11582

CPC classification number: G11C7/12 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/18 ,  H01L27/11582 ,  H01L28/00

Abstract: The present disclosure may provide a memory device including a page buffer and bit-lines coupled thereto with a less load of the bit-lines. In one aspect of the present disclosure, there is provided a memory device comprising: bit-lines, each bit-line having opposite first and second ends; plugs coupled respectively to the bit-lines, each plug disposed between and excluding the first and second ends; and a page buffer coupled to the plugs.

公开(公告)号：US09972368B2

公开(公告)日：2018-05-15

申请号：US15283011

申请日：2016-09-30

Applicant: Altera Corporation

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Ping-Chen Liu ,  Thien Le

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/10 ,  G11C5/06 ,  G11C11/412 ,  G11C11/419 ,  H03K19/17736

Abstract: Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations in the memory mode, the configuration ports may be gated off to prevent existing user data from being accessed. Each column of memory cells may be arranged into groups. Each group of memory cells in a column may be connected to a respective local data line, which is connected to a global data line via a switch. The switch may be selectively activated to short the local data line to the global data line. Configured in this hierarchical data line architecture, leakage at the global data line can dramatically be reduced, and the memory cell read margin is improved.

公开(公告)号：US20180122779A1

公开(公告)日：2018-05-03

申请号：US15699750

申请日：2017-09-08

Applicant: Intel Corporation

Inventor： Pete D. VOGT ,  Andre SCHAEFER ,  Warren MORROW ,  John B. HALBERT ,  Jin KIM ,  Kenneth D. SHOEMAKER

IPC: H01L25/065 ,  H01L27/108 ,  H01L23/48 ,  G11C5/06 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

公开(公告)号：US20180102365A1

公开(公告)日：2018-04-12

申请号：US15729532

申请日：2017-10-10

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Julien Ryckaert ,  Hyungrock Oh

IPC: H01L27/108 ,  H01L21/8254 ,  G11C11/405

CPC classification number: H01L27/108 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01L21/8254 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/10805 ,  H01L28/60

Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

公开(公告)号：US09940292B2

公开(公告)日：2018-04-10

申请号：US15712169

申请日：2017-09-22

Applicant: Etron Technology, Inc.

Inventor： Weng-Dah Ken ,  Chao-Chun Lu ,  Jan-Mye Sung

IPC: G06F13/42 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40

CPC classification number: G06F13/4234 ,  G06F13/4018 ,  G06F13/42 ,  G11C5/06 ,  G11C8/18 ,  H01L23/544 ,  H01L23/585 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3025 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2924/00

Abstract: A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

公开(公告)号：US20180090188A1

公开(公告)日：2018-03-29

申请号：US15273744

申请日：2016-09-23

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yi-Tzu Chen ,  Anjana Singh ,  Che-Ju Yeh ,  Hau-Tai Shieh

IPC: G11C7/12 ,  G11C5/06 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C5/06 ,  G11C7/06 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/419 ,  G11C2207/002

Abstract: A memory device includes a memory cell, a local bit line, a data line, first and second pass gate circuits, and a sense amplifier. The local bit line is coupled to the memory cell. The first pass gate circuit is coupled to the local bit line and the data line and is configured to couple the local bit line to the data line. The second pass gate circuit is coupled to the data line and the global bit line and is configured to couple the data line to the global bit line. The sense amplifier is coupled to the data line.

公开(公告)号：US09929747B2

公开(公告)日：2018-03-27

申请号：US15395702

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Daniel F. Cutter ,  Kirk S. Yap

IPC: H03M7/38 ,  H03M7/40 ,  H04L29/06 ,  H03M7/30

CPC classification number: H04Q11/0005 ,  B25J15/0014 ,  B65G1/0492 ,  G02B6/3882 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/4292 ,  G02B6/4452 ,  G05D23/1921 ,  G05D23/2039 ,  G06F1/183 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/65 ,  G06F9/4401 ,  G06F9/5016 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5072 ,  G06F9/5077 ,  G06F11/141 ,  G06F11/3414 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F12/109 ,  G06F12/1408 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/409 ,  G06F13/42 ,  G06F13/4282 ,  G06F15/8061 ,  G06F17/30949 ,  G06F2209/5019 ,  G06F2209/5022 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/7207 ,  G06Q10/06 ,  G06Q10/06314 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/008 ,  G08C17/02 ,  G08C2200/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1072 ,  G11C11/56 ,  G11C14/0009 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/40 ,  H03M7/4031 ,  H03M7/4056 ,  H03M7/4081 ,  H03M7/6005 ,  H03M7/6023 ,  H04B10/25 ,  H04B10/2504 ,  H04L9/0643 ,  H04L9/14 ,  H04L9/3247 ,  H04L9/3263 ,  H04L12/2809 ,  H04L29/12009 ,  H04L41/024 ,  H04L41/046 ,  H04L41/0813 ,  H04L41/082 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/145 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/08 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/765 ,  H04L47/782 ,  H04L47/805 ,  H04L47/82 ,  H04L47/823 ,  H04L49/15 ,  H04L49/25 ,  H04L49/357 ,  H04L49/45 ,  H04L49/555 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H04L67/16 ,  H04L67/306 ,  H04L67/34 ,  H04L69/04 ,  H04L69/329 ,  H04Q1/04 ,  H04Q11/00 ,  H04Q11/0003 ,  H04Q11/0062 ,  H04Q11/0071 ,  H04Q2011/0037 ,  H04Q2011/0041 ,  H04Q2011/0052 ,  H04Q2011/0073 ,  H04Q2011/0079 ,  H04Q2011/0086 ,  H04Q2213/13523 ,  H04Q2213/13527 ,  H04W4/023 ,  H04W4/80 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0204 ,  H05K7/1418 ,  H05K7/1421 ,  H05K7/1422 ,  H05K7/1447 ,  H05K7/1461 ,  H05K7/1485 ,  H05K7/1487 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/1498 ,  H05K7/2039 ,  H05K7/20709 ,  H05K7/20727 ,  H05K7/20736 ,  H05K7/20745 ,  H05K7/20836 ,  H05K13/0486 ,  H05K2201/066 ,  H05K2201/10121 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y10S901/01

Abstract: Technologies for high-performance single-stream data compression include a computing device that updates an index data structure based on an input data stream. The input data stream is divided into multiple chunks. Each chunk has a predetermined length, such as 136 bytes, and overlaps the previous chunk by a predetermine amount, such as eight bytes. The computing device processes multiple chunks in parallel using the index data to generate multiple token streams. The tokens include literal tokens and reference tokens that refer to matching data from earlier in the input data stream. The computing device thus searches for matching data in parallel. The computing device merges the token streams to generate a single output token stream. The computing device may merge a pair of tokens from two different chunks to generate one or more synchronized tokens that are output to the output token stream. Other embodiments are described and claimed.

公开(公告)号：US20180082719A1

公开(公告)日：2018-03-22

申请号：US15823013

申请日：2017-11-27

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Steven M. Bodily

IPC: G11C7/06 ,  G11C7/22 ,  G11C19/00 ,  G11C11/4091 ,  G11C8/10 ,  G11C5/06 ,  G11C7/10 ,  G11C7/08

CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

公开(公告)号：US09911499B2

公开(公告)日：2018-03-06

申请号：US15588848

申请日：2017-05-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kenichi Abe ,  Masanobu Shirakawa

IPC: G11C16/26 ,  G11C16/08 ,  G11C5/06 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04 ,  G11C5/02

CPC classification number: G11C11/5642 ,  G11C5/02 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2213/71 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, and first and second bit lines. The first and second bit lines are electrically connected to one ends of the first and second memory cells, respectively. In retry reading, a voltage applied to the first bit line is different from a voltage applied to the second bit line.

公开(公告)号：US09905315B1

公开(公告)日：2018-02-27

申请号：US15413429

申请日：2017-01-24

Applicant: NXP USA, INC.

Inventor： Prokash Ghosh ,  Sourav Roy ,  Neha Raj

IPC: G11C29/00 ,  G11C5/06

CPC classification number: G11C29/70 ,  G11C5/06

Abstract: An error-resilient memory device includes sets of memory blocks and redundant memory blocks for storing a set of data bits. A memory block includes a set of memory cells, each memory cell is adjacent to at least two other memory cells, and a memory block is formed by a matrix of the set of memory cells. In a row-folded implementation, a word line is connected to each memory cell, and a set of bit lines is connected to the corresponding set of memory cells. In a column-folded implementation, a bit line is connected to each memory cell, and a set of word lines is connected to the corresponding set of memory cells. A redundant memory block is used to store the set of data bits when the memory block includes a fault.