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公开(公告)号：US20160172494A1
公开(公告)日：2016-06-16
申请号：US15051724
申请日：2016-02-24
Inventor： JHON-JHY LIAW
IPC: H01L29/78 , H01L27/112 , H01L29/66 , H01L29/786 , H01L29/06
CPC classification number: H01L29/7841 , H01L27/11273 , H01L27/2454 , H01L29/0676 , H01L29/66742 , H01L29/7827 , H01L29/78642
Abstract: A memory device includes a substrate and a memory array. The substrate has a continuous active region. The memory array is disposed in the continuous active region of the substrate and includes a plurality of memory cells, each of which includes a transistor. The transistor has a nano-scaled pillar that extends substantially vertically from the continuous active region of the substrate.
Abstract translation: 存储器件包括衬底和存储器阵列。 衬底具有连续的有源区。 存储器阵列设置在衬底的连续有源区中，并且包括多个存储单元，每个存储单元包括晶体管。 晶体管具有从衬底的连续有源区基本垂直延伸的纳米级柱。
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公开(公告)号：US09368555B2
公开(公告)日：2016-06-14
申请号：US14178636
申请日：2014-02-12
Applicant: Kabushiki Kaisha Toshiba
Inventor： Takamasa Okawa , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno , Atsushi Yoshida , Hideyuki Tabata
CPC classification number: H01L27/249 , G11C13/0002 , G11C13/0026 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/2454 , H01L45/04 , H01L45/12 , H01L45/1226 , H01L45/146
Abstract: This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.
Abstract translation: 该半导体存储器件包括存储单元阵列，其包括：多个第一线; 与所述多个第一线相交的多个第二线; 多个存储单元，各自设置在所述多个第一线和所述多条第二线的交点处，并且包括可变电阻元件; 以及选择晶体管，其分别连接到所述多条第一线的端部。 选择晶体管包括栅电极，栅极绝缘膜和导电层。 此外，该导电层的一端连接到第一线的端部，并且由第一线和导电层之间连接由非线性材料构成的非线性电阻层。
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公开(公告)号：US20160155829A1
公开(公告)日：2016-06-02
申请号：US15003679
申请日：2016-01-21
Applicant: Micron Technology, Inc.
Inventor： Kamal M. Karda , Gurtej S. Sandhu , Chandra Mouli
IPC: H01L29/66 , H01L29/786
CPC classification number: H01L45/1206 , H01L21/02532 , H01L21/02568 , H01L23/535 , H01L27/115 , H01L27/228 , H01L27/2454 , H01L29/12 , H01L29/267 , H01L29/66666 , H01L29/66969 , H01L29/66977 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78681 , H01L29/78696 , H01L43/02 , H01L43/10 , H01L45/142 , H01L45/143
Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.
Abstract translation: 一些实施例包括具有漏极区域和源极区域的晶体管。 导电栅极位于源区和漏区之间。 第一通道材料位于栅极和源极区域之间。 第一通道材料通过一种或多种绝缘材料与栅极间隔开。 第二通道材料位于第一通道材料和源极区之间，并直接接触源区。 第一和第二通道材料是过渡金属硫族化物。 源区和漏区中的一个是孔储存区，另一个是电子储存区。 隧道介电材料可以在第一和第二通道材料之间。
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公开(公告)号：US20160141416A1
公开(公告)日：2016-05-19
申请号：US15003246
申请日：2016-01-21
Applicant: Micron Technology, Inc.
Inventor： Marcello Mariani , Carlo Pozzi
IPC: H01L29/78 , H01L27/115 , H01L29/792 , H01L27/24 , H01L29/788 , H01L29/74 , H01L27/108
CPC classification number: H01L29/7827 , H01L21/2815 , H01L27/10805 , H01L27/11521 , H01L27/11568 , H01L27/2454 , H01L29/0649 , H01L29/0653 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/66363 , H01L29/66666 , H01L29/74 , H01L29/7889 , H01L29/7926
Abstract: Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.
Abstract translation: 描述了制造垂直装置的方法以及包括它们的装置和系统。 在一种这样的方法中，垂直装置至少部分地形成在第一介电材料和第二介电材料的空隙中。 还描述了另外的实施例。
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75.发明申请MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINE SELECT TRANSISTORS AND METHODS THERFOR 有权具有STAGGERED垂直位线选择晶体管的单个三维存储器阵列及其方法公开(公告)号：US20160141334A1
公开(公告)日：2016-05-19
申请号：US14542213
申请日：2014-11-14
Applicant: SanDisk 3D LLC
Inventor： Seje Takaki , Yoshio Mori
CPC classification number: H01L27/249 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L45/04 , H01L45/1226 , H01L45/146
Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors.
Abstract translation: 提供了一种单片三维存储器阵列，其包括设置在衬底上方的多个全局位线，每个全局位线具有长轴，设置在全局位线上方的多个垂直取向的位线，多个字 设置在全局位线之上的线，耦合在垂直取向的位线和字线之间的多个存储单元，以及耦合在垂直取向的位线和全局位线之间的多个垂直取向的位线选择晶体管 每个垂直取向的位线选择晶体管包括宽度和厚度。 设置在相邻全局位线之上的垂直取向的位线选择晶体管沿着全局位线的长轴的方向彼此偏移。 每个垂直取向的位线选择晶体管的宽度大于垂直取向的位线选择晶体管的厚度。
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Patent Agency Ranking
76.发明授权Dual channel vertical field effect transistor including an embedded electrode 有权双通道垂直场效应晶体管包括一个嵌入式电极公开(公告)号：US09343507B2
公开(公告)日：2016-05-17
申请号：US14206196
申请日：2014-03-12
Applicant: SanDisk 3D LLC
Inventor： Seje Takaki
IPC: H01L29/76 , H01L27/24 , H01L29/78 , H01L29/66 , H01L27/115 , H01L29/788 , H01L27/112 , H01L29/792 , H01L29/423 , H01L29/10 , H01L45/00 , H01L29/49
CPC classification number: H01L27/2481 , H01L27/11273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/1033 , H01L29/42356 , H01L29/4925 , H01L29/4983 , H01L29/66666 , H01L29/7827 , H01L29/7889 , H01L29/7926 , H01L45/04 , H01L45/1226 , H01L45/146
Abstract: A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source. Each field effect transistor may include a first channel and a second channel, each including a second conductivity type
Abstract translation: 公开了一种包括一个或多个场效应晶体管的器件，每个场效应晶体管包括：细长的漏极接触线，包括沿着第一水平方向延伸的导电材料; 漏极，包括覆盖所述漏极接触线的第一导电类型半导体区域; 源极，包括位于漏极上方的第一导电类型半导体区域; 以及在漏极和源极之间垂直延伸的栅极。 每个场效应晶体管可以包括第一通道和第二通道，每个通道包括第二导电类型
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77.发明授权Variable resistive memory device including vertical channel PMOS transistor 有权可变电阻存储器件包括垂直沟道PMOS晶体管公开(公告)号：US09299805B2
公开(公告)日：2016-03-29
申请号：US14792260
申请日：2015-07-06
Applicant: SK hynix Inc.
Inventor： Nam Kyun Park
CPC classification number: H01L29/66666 , H01L27/228 , H01L27/2454 , H01L29/1054 , H01L29/1608 , H01L29/2003 , H01L29/7827
Abstract: A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. The inner portion of the vertical pillar has a lattice constant smaller than that of the outer portion of the vertical pillar.
Abstract translation: 提供具有垂直通道的半导体器件，包括该半导体器件的可变电阻存储器件及其制造方法。 具有垂直通道的半导体器件包括：形成在半导体衬底上的垂直柱，其包括内部部分和围绕内部部分的外部部分，形成在垂直柱体的外部部分的接合部分和形成为围绕垂直方向 支柱。 垂直柱的内部具有比垂直柱的外部部分小的晶格常数。
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公开(公告)号：US09281472B2
公开(公告)日：2016-03-08
申请号：US14487847
申请日：2014-09-16
Applicant: Unisantis Electronics Singapore Pte. Ltd.
Inventor： Fujio Masuoka , Hiroki Nakamura
CPC classification number: H01L45/1608 , H01L27/2436 , H01L27/2454 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/124 , H01L45/1253 , H01L45/126 , H01L45/16 , H01L45/1675 , H01L45/1691
Abstract: The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film.
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公开(公告)号：US20160064452A1
公开(公告)日：2016-03-03
申请号：US14594782
申请日：2015-01-12
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor： Yoshihiro UEDA , Tsukasa NAKAI , Masaki KONDO , Hikari TAJIMA , Hiroki TOKUHIRA , Takashi IZUMIDA
CPC classification number: G11C13/0069 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5635 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C16/349 , G11C2213/74 , G11C2213/79 , G11C2213/82 , H01L27/228 , H01L27/2454
Abstract: A memory device according to an embodiment includes a memory element; and a transistor including a semiconductor layer and a plurality of gates, wherein the plurality of gates include: a first set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, and a second set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, the gates included in the first set is disposed in a manner to separate from the gates included in the second set in a direction along a side surface of the semiconductor layer.
Abstract translation: 根据实施例的存储器件包括存储元件; 以及包括半导体层和多个栅极的晶体管，其中所述多个栅极包括：第一组栅极，所述栅极以夹持所述半导体层的方式设置，以及第二组栅极，所述栅极被布置 以夹着半导体层的方式，包括在第一组中的栅极以沿着半导体层的侧表面的方向与包括在第二组中的栅极分离的方式设置。
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公开(公告)号：US20160064072A1
公开(公告)日：2016-03-03
申请号：US14935264
申请日：2015-11-06
Applicant: SK hynix Inc.
Inventor： Nam Kyun PARK
IPC: G11C13/00
CPC classification number: H01L27/2481 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/003 , G11C2213/71 , G11C2213/74 , G11C2213/75 , G11C2213/79 , H01L23/528 , H01L27/228 , H01L27/2454 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1273 , H01L45/14 , H01L45/141 , H01L45/147 , H01L2924/0002 , H01L2924/00
Abstract: A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.
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