公开(公告)号：US20130161782A1

公开(公告)日：2013-06-27

申请号：US13334650

申请日：2011-12-22

Applicant: S. Rajendran ,  Monte R. Sanchez ,  Susan M. Eshelman ,  Douglas R. Gentry ,  Thomas A. Hanft

Inventor： S. Rajendran ,  Monte R. Sanchez ,  Susan M. Eshelman ,  Douglas R. Gentry ,  Thomas A. Hanft

IPC: H01L27/06 ,  H01L21/762

CPC classification number: H01L23/142 ,  H01L23/043 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/488 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/92244 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Abstract translation: 通过自适应图案形成的低损耗互连将半导体部件与衬底集成，包括在衬底中形成空腔，将半导体部件放置在其中，用与之相同或相似的介电常数的填充物填充半导体部件和衬底之间的间隙 并且自适应地对填充物上的低损耗互连进行图案化并且在半导体部件的触点与衬底上的电迹线之间延伸。 触点和引线使用自适应图案化技术来定位和邻接，所述自适应图案化技术放置并形成低损耗射频传输线，其补偿半导体部件触点和衬底引线之间的任何未对准。

公开(公告)号：US20120313259A1

公开(公告)日：2012-12-13

申请号：US13156808

申请日：2011-06-09

Applicant: Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

Inventor： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC: H01L23/52 ,  H01L21/28 ,  H01L21/50 ,  H01L21/304

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

Abstract: A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.

Abstract translation: 分层芯片封装包括主体和布线。 主体有一个主要部分。 主要部分具有顶表面和底表面，并且包括堆叠的多个层部分。 布线包括穿过所有多个层部分的多条线。 各层部分包括半导体芯片和多个电极。 半导体芯片具有第一表面和与其相对的第二表面。 多个电极设置在半导体芯片的第一表面的一侧。 多个层部分包括两对或更多对第一和第二层部分，其中每个第一和第二层部分中的第一和第二层部分被布置成使得各个半导体芯片的第一或第二表面彼此面对。 多个电极包括多个第一连接部和多个第二连接部。 在第一层部分中，多个第一连接部分与多条线接触。 在第二层部分中，多个第二连接部分与多条线接触。

公开(公告)号：US20110223695A1

公开(公告)日：2011-09-15

申请号：US12835914

申请日：2010-07-14

Applicant: Kong-Chen Chen

Inventor： Kong-Chen Chen

IPC: H01L21/66

CPC classification number: H01L24/81 ,  H01L22/32 ,  H01L22/34 ,  H01L23/04 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/7532 ,  H01L2224/75703 ,  H01L2224/75753 ,  H01L2224/75988 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

Abstract: The present invention provides systems and methods for assembling an electronic assembly using an anisotropic conducting membrane (ACM) as a component interconnect and a substrate embossed with placement cavities or a positional fixture to facilitate component placement on the substrate in the electronic assembly. The fixture may comprise multiple layers of interconnects to improve routing density for the electronic assembly enclosed in a housing. An alignment chain may be used to monitor positional and contact integrity of the ACM interfaced components in a complex assembly. The systems and methods allow components to be detached for reuse. Interconnection elements or conduction pathways at the components can be used to interconnect a plurality of neighboring substrates over the ACM layers into a stacked electronic assembly.

公开(公告)号：US12074152B2

公开(公告)日：2024-08-27

申请号：US17410053

申请日：2021-08-24

Applicant: Samsung Display Co., LTD.

Inventor： Dae Hyuk Im ,  Sun Oh Jeong ,  So Young Yeo ,  Hee Ju Woo

IPC: H01L25/18 ,  H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L25/18 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/32 ,  H01L24/83 ,  H05K1/0268 ,  H01L2224/06165 ,  H01L2224/32227 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83851 ,  H01L2224/83908 ,  H05K1/189 ,  H05K2201/10128 ,  H05K2201/10378

Abstract: A display device includes a display panel, a first film attached to the display panel, an adhesive member interposed between the display panel and the first film and extending in a first direction to attach the display panel to the first film, a first test electrode covered by the adhesive member; a second test electrode covered by the adhesive member and spaced apart from the first test electrode in a second direction perpendicular to the first direction, and test lines comprising a first test line electrically connected to the first test electrode and a second test line electrically connected to the second test electrode, where the adhesive member is disposed between the first test electrode and the second test electrode in the second direction.

公开(公告)号：US20240164022A1

公开(公告)日：2024-05-16

申请号：US17915707

申请日：2021-11-01

Applicant: BOE MLED Technology Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jing WANG ,  Mingming JIA ,  Lili WANG ,  Sha FENG ,  Chao LIU ,  Ming ZHAI ,  Haiwei SUN ,  Lingyun SHI ,  Liqiang WANG ,  Jingjing ZHANG

IPC: H05K1/18 ,  H01L23/00 ,  H01L25/075 ,  H05K1/11

CPC classification number: H05K1/189 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/83 ,  H05K1/118 ,  H01L25/0753 ,  H01L2224/05573 ,  H01L2224/06155 ,  H01L2224/32225 ,  H01L2224/8313 ,  H01L2224/83201 ,  H05K2201/056 ,  H05K2201/10128

Abstract: A display module includes a display panel with a plurality of bonding electrodes arranged at intervals along a selected side edge of a non-display surface and divided into two bonding electrode groups, a first flexible circuit board and a second flexible circuit board. For the first flexible circuit board, each first conductive contact piece in a first wiring region is connected to a bonding electrode in a first bonding electrode group. For the second flexible circuit board, each second conductive contact piece in a second wiring region is connected to a bonding electrode in a second bonding electrode group. The first wiring region is closer to the selected side edge than the second wiring region in a first direction. The first fan-out region is spaced apart from the second wiring region in a second direction perpendicular to the first direction.

公开(公告)号：US11721637B2

公开(公告)日：2023-08-08

申请号：US16884437

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Ping-Yin Liu

IPC: H01L23/544 ,  H01L23/00 ,  B23Q17/22 ,  H01L21/18 ,  H01L21/68

CPC classification number: H01L23/544 ,  H01L24/83 ,  B23Q17/22 ,  H01L21/187 ,  H01L21/681 ,  H01L2223/54426 ,  H01L2224/8313

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.

公开(公告)号：US11664364B2

公开(公告)日：2023-05-30

申请号：US17212620

申请日：2021-03-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0384 ,  H01L2224/03831 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/0603 ,  H01L2224/06517 ,  H01L2224/0801 ,  H01L2224/08146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/32145 ,  H01L2224/8013 ,  H01L2224/8092 ,  H01L2224/80895 ,  H01L2224/80951 ,  H01L2224/8313 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2225/06544

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.

公开(公告)号：US09935079B1

公开(公告)日：2018-04-03

申请号：US15372482

申请日：2016-12-08

Applicant: NXP USA, Inc.

Inventor： Chee Seng Foong ,  Trent Uehling ,  Leo M. Higgins, III

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L24/83 ,  H01L21/4853 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L25/0655 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/16227 ,  H01L2224/27505 ,  H01L2224/32137 ,  H01L2224/8313 ,  H01L2224/8384 ,  H01L2924/2075

Abstract: Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.

公开(公告)号：US20180026012A1

公开(公告)日：2018-01-25

申请号：US15543397

申请日：2016-01-13

Applicant: DEXERIALS CORPORATION

Inventor： Yasushi AKUTSU ,  Tomoyuki ISHIMATSU

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/133 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17107 ,  H01L2224/17181 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27515 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81122 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81203 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83122 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00015 ,  H01L2924/3841 ,  H01L2224/83851 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2924/05432

Abstract: Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive.

公开(公告)号：US09673168B2

公开(公告)日：2017-06-06

申请号：US15114453

申请日：2015-02-03

Applicant: DEXERIALS CORPORATION

Inventor： Kenichi Saruyama ,  Yasushi Akutsu

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/29293 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/2936 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81488 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83499 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/0549 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/069 ,  H01L2924/0635 ,  H01L2924/01006

Abstract: Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c≦0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles.