公开(公告)号：US20240014152A1

公开(公告)日：2024-01-11

申请号：US17811132

申请日：2022-07-07

申请人： NXP B.V.

发明人： Leo van Gemert ,  Jeroen Johannes Maria Zaal

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L24/04 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03632 ,  H01L2224/03462 ,  H01L2224/03914 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05083 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05573 ,  H01L2224/05561 ,  H01L2224/05572 ,  H01L2224/03013 ,  H01L2224/02145 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05164 ,  H01L2224/05147 ,  H01L24/13 ,  H01L2224/13144 ,  H01L2224/13147

摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a non-conductive layer over an active side of a semiconductor die partially encapsulated with an encapsulant. An opening in the non-conductive layer is formed exposing a portion of a bond pad of the semiconductor die. A laser ablated trench is formed at a surface of the non-conductive layer proximate to a perimeter of the opening. A bottom surface of the laser ablated trench is substantially roughened. An under-bump metallization (UBM) structure is formed over the bond pad and laser ablated trench.

公开(公告)号：US20240006400A1

公开(公告)日：2024-01-04

申请号：US17856965

申请日：2022-07-02

申请人： Intel Corporation

发明人： Kyle J. Arrington ,  Karumbu Nathan Meyyappan ,  Srikant Nekkanty

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L25/18 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13105 ,  H01L2224/13139 ,  H01L2224/13169 ,  H01L2224/13144 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/81405 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2924/01008 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L24/29

摘要： In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).

公开(公告)号：US20240006278A1

公开(公告)日：2024-01-04

申请号：US18200590

申请日：2023-05-23

申请人： MEDIATEK INC.

发明人： Hsin-Long Chen ,  Chin-Chiang Chang

IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H10B80/00 ,  H01L23/00

CPC分类号： H01L23/49805 ,  H01L25/0657 ,  H01L23/3107 ,  H10B80/00 ,  H01L24/48 ,  H01L24/73 ,  H01L24/32 ,  H01L24/16 ,  H01L24/45 ,  H01L2924/1436 ,  H01L2224/32245 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48011 ,  H01L2224/13147 ,  H01L2924/1433

摘要： A multi-die QFN hybrid package includes a carrier having flip-chip leads and wire-bonding leads. A first die and a second die are mounted on the flip-chip leads, respectively, in a flip-chip manner. The first die is spaced apart from the second die. A third die is stacked over the first die and the second die. The third die is electrically connected to the wire-bonding leads around the first die and the second die through bond wires. A mold cap encapsulates the first die, the second die, the third die, the bond wires, and partially encapsulates the carrier. The flip-chip leads and the wire-bonding leads are exposed from a bottom mold cap surface.

公开(公告)号：US20230420403A1

公开(公告)日：2023-12-28

申请号：US18165419

申请日：2023-02-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyeonjun Song ,  Jungmin Ko ,  Taehyeong Kim ,  Youngwoo Lim ,  Dongki Choi

IPC分类号： H01L23/00 ,  H01L25/18 ,  H01L23/31

CPC分类号： H01L24/32 ,  H01L25/18 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/73 ,  H01L24/83 ,  H01L24/13 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/83007 ,  H01L2224/26125 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13113 ,  H01L2224/13118

摘要： A semiconductor package includes a base chip; semiconductor chips stacked on the base chip; bumps, a lowermost bump of the bumps disposed between the base chip and a lowermost semiconductor chip of the semiconductor chips, and each of the bumps except the lowermost bump respectively disposed between the semiconductor chips; organic material layers, a lowermost organic material layer of the organic material layers disposed between the base chip and the lowermost semiconductor chip, and each of organic material layers except the lowermost organic material layer respectively disposed between the plurality of semiconductor chips; underfill layers respectively surrounding the plurality of bumps, the underfill layers extending between the base chip and the lowermost semiconductor chip and between the semiconductor chips; and an encapsulant covering the base chip, the semiconductor chips, and the underfill layers.

公开(公告)号：US11855333B2

公开(公告)日：2023-12-26

申请号：US17874252

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC分类号： H01Q1/22 ,  H01L23/31 ,  H01Q21/06 ,  H01Q1/38 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/66 ,  H01Q9/04 ,  H01L21/56

CPC分类号： H01Q1/2283 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/528 ,  H01L23/66 ,  H01L24/14 ,  H01L24/82 ,  H01Q1/38 ,  H01Q9/04 ,  H01Q21/065 ,  H01L21/568 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/18 ,  H01L2924/1431 ,  H01L2924/1431 ,  H01L2924/00012

摘要： Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

公开(公告)号：US11855025B2

公开(公告)日：2023-12-26

申请号：US16687089

申请日：2019-11-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chita Chuang ,  Yao-Chun Chuang ,  Tsung-Shu Lin ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L23/3192 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/1147 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13005 ,  H01L2224/1308 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/206 ,  H01L2924/381 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/05186 ,  H01L2924/04953 ,  H01L2224/05005 ,  H01L2924/206 ,  H01L2224/05541 ,  H01L2924/206 ,  H01L2224/05647 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/01024 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/01079 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/01025 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/01024 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/01022 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/01032 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/01078 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/01012 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/01013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/0104 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/13005 ,  H01L2924/206 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2224/13169 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/00014 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor device includes a conductive pad having a first width. The semiconductor device includes a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad. The semiconductor device includes a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The semiconductor device includes an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device includes a conductive pillar on the UBM layer.

公开(公告)号：US11855015B2

公开(公告)日：2023-12-26

申请号：US17468871

申请日：2021-09-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Chi Huang ,  Chang-Yao Huang ,  Po-Cheng Chen

IPC分类号： H01L23/00 ,  G03F7/00

CPC分类号： H01L24/02 ,  G03F7/70925 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0215 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/11462 ,  H01L2224/13005 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2924/07025 ,  H01L2924/2064 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754

摘要： A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

公开(公告)号：US11854945B2

公开(公告)日：2023-12-26

申请号：US16228378

申请日：2018-12-20

申请人： Tahoe Research, Ltd.

发明人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Rajendra C. Dias ,  Edvin Cetegen ,  Lars D. Skoglund

IPC分类号： H01L23/485 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/485 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81203 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665

摘要： Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

公开(公告)号：US20230411347A1

公开(公告)日：2023-12-21

申请号：US18267492

申请日：2021-12-14

申请人： THE UNIVERSITY OF HONG KONG

发明人： Mingxin Huang ,  Shien Ping Feng

IPC分类号： H01L23/00

CPC分类号： H01L24/83 ,  H01L24/13 ,  H01L2224/83203 ,  H01L2924/01029 ,  H01L2224/13147 ,  H01L2224/29147 ,  H01L2224/8309

摘要： Disclosed is a method of bonding two copper structures involving compressing a first copper structure with a second copper structure under a stress from 0.1 MPa to 50 MPa and under a temperature of 250° C. or less so that a bonding surface of the first copper structure is bonded to a bonding surface of the second copper structure; at least one of the bonding surface of the first copper structure and the bonding surface of the second copper structure have a layer of nanograins of copper having an average grain size of 5 nm to 500 nm, the layer of the nanograins of copper having a thickness of 10 nm to 10 μm.

公开(公告)号：US20230411235A1

公开(公告)日：2023-12-21

申请号：US18209470

申请日：2023-06-13

申请人： STATS ChipPac Semiconductor (Jiangyin) Co., LTD.

发明人： MAN BAO ,  WEIJUN WANG

IPC分类号： H01L23/367 ,  H01L25/16 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/3675 ,  H01L25/16 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L21/4871 ,  H01L2224/13155 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29166 ,  H01L2224/32245 ,  H01L2224/33051 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/165

摘要： The present invention discloses an elastic heat spreader for chip packaging, a packaging structure and a packaging method. The heat spreader includes a top cover plate and a side cover plate that extends outward along an edge of the top cover plate, wherein the top cover plate is configured to be placed on a chip, and at least a partial region of the side cover plate is an elastic member; and the elastic member at least enables the side cover plate to be telescopic in a direction perpendicular to the top cover plate. According to the present invention, a following problem is solved: delamination between the heat spreader and a substrate as well as the chip due to stress generated by different thermal expansion coefficients of the substrate, the heat spreader and the chip in a packaging process of a large-size product.