公开(公告)号：US20220399263A1

公开(公告)日：2022-12-15

申请号：US17345912

申请日：2021-06-11

申请人： Intel Corporation

发明人： Brandon Christian Marin ,  Tarek A. Ibrahim ,  Karumbu Nathan Meyyappan ,  Valery Ouvarov-Bancalero ,  Dingying Xu

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

公开(公告)号：US20230314503A1

公开(公告)日：2023-10-05

申请号：US17709630

申请日：2022-03-31

申请人： Intel Corporation

发明人： Gregorio Roberto Murtagian ,  Karumbu Nathan Meyyappan

IPC分类号： G01R31/28 ,  G01R1/04

CPC分类号： G01R31/2889 ,  G01R31/2853 ,  G01R1/0483 ,  G01R31/2896 ,  H01L27/0886

摘要： Technologies for testing integrated circuit components with liquid metal interconnects are disclosed. In the illustrative embodiment, a bed of nails adapter can mate with an integrated circuit component with liquid metal interconnects. The nails pierce a sealing cap layer that seals the liquid metal interconnects, electrically coupling the nails to the liquid metal interconnects. An underside of the bed of nails adapter has an array of pads that are coupled to the nails. The array of pads may be used to mate the bed of nails adapter and integrated circuit component with several land grid array sockets for testing of the integrated circuit component. As the bed of nails adapter does not need to be removed as the integrated circuit component is moved to a new land grid array socket, the number of times the sealing cap layer is pierced by nails during testing is reduced.

公开(公告)号：US20240074046A1

公开(公告)日：2024-02-29

申请号：US17899336

申请日：2022-08-30

申请人： Intel Corporation

发明人： Ziyin Lin ,  Karumbu Nathan Meyyappan ,  Dingying Xu

IPC分类号： H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC分类号： H05K1/11 ,  H05K1/181 ,  H05K3/46 ,  H05K2201/0302 ,  H05K2201/10378

摘要： Technologies for integrated circuit components with liquid metal interconnects are disclosed. In the illustrative embodiment, a bed of nails socket can mate with an integrated circuit component with liquid metal interconnects. The nails pierce a foam cap layer that seals the liquid metal interconnects, electrically coupling the nails to the liquid metal interconnects. A fabric layer adjacent to the foam cap layer helps secure the foam cap layer, preventing small pieces of the foam cap layer that may be dislodged during repeated insertion into a bed of nails socket from becoming separated from the foam cap layer. The fabric layer can provide additional benefits, such as removing more of the liquid metal from the nails when the integrated circuit component is removed from the bed of nails socket.

公开(公告)号：US20240006400A1

公开(公告)日：2024-01-04

申请号：US17856965

申请日：2022-07-02

申请人： Intel Corporation

发明人： Kyle J. Arrington ,  Karumbu Nathan Meyyappan ,  Srikant Nekkanty

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L25/18 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13105 ,  H01L2224/13139 ,  H01L2224/13169 ,  H01L2224/13144 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/81405 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2924/01008 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L24/29

摘要： In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).

公开(公告)号：US20230317619A1

公开(公告)日：2023-10-05

申请号：US17711978

申请日：2022-04-01

申请人： Intel Corporation

发明人： Ravindranath V. Mahajan ,  Srikant Nekkanty ,  Srinivas V. Pietambaram ,  Veronica Strong ,  Xiao Lu ,  Tarek A. Ibrahim ,  Karumbu Nathan Meyyappan ,  Dingying Xu ,  Kristof Darmawikarta

IPC分类号： H01L23/538 ,  H01L21/48

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L23/5384

摘要： A microelectronic structure, a semiconductor package including the same, and a method of forming same. The microelectronic structures includes: a substrate defining a cavity therein; a bridge die within the cavity, the bridge die to electrically couple a pair of dies to be provided on a surface of the substrate; an electrical coupling layer between a top surface of the cavity and a bottom surface of the bridge die. The electrical coupling layer includes: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.

公开(公告)号：US20230317533A1

公开(公告)日：2023-10-05

申请号：US17710556

申请日：2022-03-31

申请人： Intel Corporation

发明人： Gregorio Roberto Murtagian ,  Karumbu Nathan Meyyappan ,  Valery Ouvarov-Bancalero

IPC分类号： H01L23/22 ,  H01L23/498

CPC分类号： H01L23/22 ,  H01L23/49827 ,  H01L23/49816

摘要： Technologies for liquid metal mixtures for electrical interconnects are disclosed. In the illustrative embodiment, a gallium mixture includes gallium or gallium alloy mixed with fine particles of, e.g., gallium oxide. The fine particles change properties of the gallium or gallium alloy, such as the viscosity, surface tension, and surface bonding. As a result of the changes caused by the fine particles, the gallium mixture can be more easily integrated into electrical interconnects, such as by using screen printing techniques. In one embodiment, the gallium mixture may form an array of interconnects on an integrated circuit component for connecting to another integrated circuit component.