公开(公告)号：US12183595B2

公开(公告)日：2024-12-31

申请号：US18064641

申请日：2022-12-12

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Peter Joseph Hubert Drummen

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/66

Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

公开(公告)号：US11963291B2

公开(公告)日：2024-04-16

申请号：US17726426

申请日：2022-04-21

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Michael B. Vincent

IPC: H05K1/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01P3/12 ,  H05K1/11 ,  H05K3/10 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/0243 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01P3/121 ,  H05K1/0218 ,  H05K1/111 ,  H05K3/10 ,  H05K3/3426 ,  H05K3/4007 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/1903 ,  H05K2201/10734

Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.

公开(公告)号：US20240014152A1

公开(公告)日：2024-01-11

申请号：US17811132

申请日：2022-07-07

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Jeroen Johannes Maria Zaal

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L24/04 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03632 ,  H01L2224/03462 ,  H01L2224/03914 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05083 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05573 ,  H01L2224/05561 ,  H01L2224/05572 ,  H01L2224/03013 ,  H01L2224/02145 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05164 ,  H01L2224/05147 ,  H01L24/13 ,  H01L2224/13144 ,  H01L2224/13147

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a non-conductive layer over an active side of a semiconductor die partially encapsulated with an encapsulant. An opening in the non-conductive layer is formed exposing a portion of a bond pad of the semiconductor die. A laser ablated trench is formed at a surface of the non-conductive layer proximate to a perimeter of the opening. A bottom surface of the laser ablated trench is substantially roughened. An under-bump metallization (UBM) structure is formed over the bond pad and laser ablated trench.

公开(公告)号：US11508669B2

公开(公告)日：2022-11-22

申请号：US16557181

申请日：2019-08-30

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Jeroen Johannes Maria Zaal ,  Michiel van Soestbergen ,  Romuald Olivier Nicolas Roucou

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  G06F30/394 ,  G06F30/398 ,  G06F113/18 ,  G06F119/08

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

公开(公告)号：US10315821B2

公开(公告)日：2019-06-11

申请号：US15352214

申请日：2016-11-15

Applicant: NXP B.V.

Inventor： Jeroen Johannes Maria Zaal ,  Roelf Anco Jacob Groenhuis ,  Leo van Gemert ,  Caroline Catharina Maria Beelen-Hendrikx

IPC: B65D73/02 ,  H01L21/683 ,  H01L23/06 ,  H01L23/053

Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.

公开(公告)号：US20210134612A1

公开(公告)日：2021-05-06

申请号：US16669579

申请日：2019-10-31

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Peter Joseph Hubert Drummen

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/552 ,  H01L23/66 ,  H01L21/48

Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

公开(公告)号：US20210066209A1

公开(公告)日：2021-03-04

申请号：US16557181

申请日：2019-08-30

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Jeroen Johannes Maria Zaal ,  Michiel van Soestbergen ,  Romuald Olivier Nicolas Roucou

IPC: H01L23/00 ,  G06F17/50 ,  H01L23/498 ,  H01L23/66

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

公开(公告)号：US20170148697A1

公开(公告)日：2017-05-25

申请号：US15342285

申请日：2016-11-03

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Leo van Gemert ,  Hans van Rijckevorsel ,  Sascha Moeller ,  Hartmut Buenning ,  Steffen Holland ,  Y Kuang Huang

IPC: H01L23/31 ,  H01L29/06 ,  H01L23/00 ,  H01L21/3205 ,  H01L21/683 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/32051 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/528 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10156 ,  H01L2924/17747 ,  H01L2924/35 ,  H01L2924/37

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

公开(公告)号：US20240154300A1

公开(公告)日：2024-05-09

申请号：US18496975

申请日：2023-10-30

Applicant: NXP B.V.

Inventor： Harshitha Thippur Shivamurthy ,  Rabia Syeda ,  Rocío Gabriela Molina Moreno ,  Cristine Aguila Badiao ,  Pieter Lok ,  Adrianus Buijsman ,  Leo van Gemert ,  Maarten Lont ,  Giorgio Carluccio ,  Antonius Johannes Matheus de Graauw

IPC: H01Q1/38 ,  H01Q1/22

CPC classification number: H01Q1/38 ,  H01Q1/2283

Abstract: A system comprising: a waveguide assembly comprising a plurality of waveguides, the plurality of waveguides comprising at least a first waveguide and a second waveguide, and an integrated circuit package, IC package, comprising a plurality of launchers to one or more of transmit signalling to and receive signalling from a respective one of the plurality of waveguides, wherein the waveguide assembly comprises a surface configured to be coupled to the IC package and each of the plurality of waveguides comprises an opening in the surface configured to be aligned with its respective launcher, and wherein each of the openings has a major dimension and a minor dimension, wherein the major dimension is larger than the minor dimension, and wherein the major dimension of at least the opening of the first waveguide is oriented perpendicular to the major dimension of the opening of the second waveguide.

公开(公告)号：US20230345623A1

公开(公告)日：2023-10-26

申请号：US17726426

申请日：2022-04-21

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Michael B. Vincent

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K3/10 ,  H05K3/40 ,  H01P3/12 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L21/56

CPC classification number: H05K1/0243 ,  H05K1/111 ,  H05K1/0218 ,  H05K3/3426 ,  H05K3/10 ,  H05K3/4007 ,  H01P3/121 ,  H01L24/16 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/66 ,  H01L21/4853 ,  H01L21/563 ,  H05K2201/10734 ,  H01L2224/16227 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2924/18161 ,  H01L2924/1903

Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.