公开(公告)号：US20230393192A1

公开(公告)日：2023-12-07

申请号：US17805555

申请日：2022-06-06

Applicant: NXP B.V.

Inventor： Michiel van Soestbergen ,  Amar Ashok Mavinkurve

IPC: G01R31/28

CPC classification number: G01R31/2889

Abstract: A device comprises a substrate and a stacked bond ball structure. The substrate comprises a bond pad, and the stacked bond ball structure comprises a first and a second bond ball. The first bond ball is in contact with the bond pad, and the second bond ball is positioned on the first bond ball. The stacked bond ball structure is configured to be coupled to a resistance-sensing circuit, such that a resistance of an interface between the first bond ball and the bond pad can be measured to determine an amount of degradation of the interface between the first bond ball and the bond pad. In some implementations, the device further comprises a controller configured to obtain a measured resistance of the interface from the resistance-sensing circuit and determine the amount of degradation of the interface based at least in part on the measured resistance.

公开(公告)号：US12061228B2

公开(公告)日：2024-08-13

申请号：US17805555

申请日：2022-06-06

Applicant: NXP B.V.

Inventor： Michiel van Soestbergen ,  Amar Ashok Mavinkurve

IPC: G01R31/28

CPC classification number: G01R31/2889

Abstract: A device comprises a substrate and a stacked bond ball structure. The substrate comprises a bond pad, and the stacked bond ball structure comprises a first and a second bond ball. The first bond ball is in contact with the bond pad, and the second bond ball is positioned on the first bond ball. The stacked bond ball structure is configured to be coupled to a resistance-sensing circuit, such that a resistance of an interface between the first bond ball and the bond pad can be measured to determine an amount of degradation of the interface between the first bond ball and the bond pad. In some implementations, the device further comprises a controller configured to obtain a measured resistance of the interface from the resistance-sensing circuit and determine the amount of degradation of the interface based at least in part on the measured resistance.

公开(公告)号：US11508669B2

公开(公告)日：2022-11-22

申请号：US16557181

申请日：2019-08-30

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Jeroen Johannes Maria Zaal ,  Michiel van Soestbergen ,  Romuald Olivier Nicolas Roucou

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  G06F30/394 ,  G06F30/398 ,  G06F113/18 ,  G06F119/08

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

公开(公告)号：US20240413192A1

公开(公告)日：2024-12-12

申请号：US18329847

申请日：2023-06-06

Applicant: NXP B.V.

Inventor： Paul Southworth ,  Michiel van Soestbergen ,  Amar Ashok Mavinkurve ,  Wen Yuan Chuang ,  Michael B. Vincent

IPC: H01L21/02

Abstract: A semiconductor device may include a semiconductor substrate and an isolation structure including a first dielectric layer formed over the semiconductor substrate, the first dielectric layer including one or more air gaps, and a first conductive structure formed on the dielectric layer, the conductive structure having a lower surface that faces the semiconductor substrate. Respective air gaps of the one or more air gaps of the first dielectric layer each may be disposed directly between corners of the lower surface of the conductive structure and the semiconductor substrate.

公开(公告)号：US20210066209A1

公开(公告)日：2021-03-04

申请号：US16557181

申请日：2019-08-30

Applicant: NXP B.V.

Inventor： Leo van Gemert ,  Jeroen Johannes Maria Zaal ,  Michiel van Soestbergen ,  Romuald Olivier Nicolas Roucou

IPC: H01L23/00 ,  G06F17/50 ,  H01L23/498 ,  H01L23/66

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.