公开(公告)号：US10177111B2

公开(公告)日：2019-01-08

申请号：US15450972

申请日：2017-03-06

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Leonardus Antonius Elisabeth van Gemert ,  Roelf Anco Jacob Groenhuis ,  Caroline Catharina Maria Beelen-Hendrikx ,  Jetse de Witte ,  Franciscus Henrikus Martinus Swartjes

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L23/544 ,  H01L21/304

Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.

公开(公告)号：US09245804B2

公开(公告)日：2016-01-26

申请号：US13967084

申请日：2013-08-14

Applicant: NXP B.V.

Inventor： Christian Zenz ,  Hartmut Buenning ,  Leonardus Antonius Elisabeth Van Gemert ,  Tonny Kamphuis ,  Sascha Moeller

IPC: H01L21/44 ,  H01L21/82 ,  H01L21/782 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/488 ,  H01L21/50 ,  H01L21/56 ,  H01L21/683 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

Abstract: Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (θ) of tooling impact upon a vertical face the semiconductor device.

Abstract translation: 与示例性实施例一致，存在半导体器件，其中有源器件具有正面和背面; 总体厚度的半导体器件包括具有限定在前侧表面上的电路的有源器件，前侧表面具有区域。 有源器件的背面具有有源器件厚度的部分深度和大约部分深度的宽度的凹部，在垂直边缘处围绕有源器件的凹部。 在有源器件的背面具有厚度的保护层，该保护材料的面积大于第一区域并具有间隔距离。 垂直边缘具有填充与垂直边缘齐平的凹部的保护层。 保护材料的间隔距离是半导体器件厚度和在半导体器件的垂直面上的工具冲击的角度（＆amp;）的切线的函数。

公开(公告)号：US20160005680A1

公开(公告)日：2016-01-07

申请号：US14322553

申请日：2014-07-02

Applicant: NXP B.V.

Inventor： Emil Casey Israel ,  Leonardus Antonius Elisabeth van Gemert ,  Tonny Kamphuis

IPC: H01L23/495 ,  H01L21/82 ,  H01L21/52

CPC classification number: H01L23/49568 ,  H01L21/52 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49548 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a heat sink array having a top-side surface and an under-side surface; the heat sink array has die placement areas on the top-side surface. A plurality of active device die are die bonded onto the die placement areas on the heat sink array. The plurality of active device die are singulated into an individual heat sink device die having a heat sink portion attached to its underside.

Abstract translation: 与示例性实施例一致，存在制备具有增强散热的集成电路（IC）装置的方法。 该方法包括提供具有顶侧表面和下侧表面的散热器阵列; 散热器阵列在顶侧表面具有管芯放置区域。 多个有源器件裸片裸片结合到散热片阵列上的管芯放置区域上。 多个有源器件管芯被分割成具有附接到其下侧的散热器部分的单个散热器器件管芯。

公开(公告)号：US09704823B2

公开(公告)日：2017-07-11

申请号：US14927283

申请日：2015-10-29

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Roelf Anco Jacob Groenhuis ,  Leonardus Antonius Elisabeth van Gemert ,  Caroline Catharina Maria Beelen-Hendrikx ,  Jetse de Witte ,  Franciscus Henrikus Martinus Swartjes

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L24/94 ,  H01L21/304 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3164 ,  H01L23/3178 ,  H01L23/544 ,  H01L24/11 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2224/11

Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.

公开(公告)号：US09379071B2

公开(公告)日：2016-06-28

申请号：US14255935

申请日：2014-04-17

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Jan Gulpen ,  Jan Willem Bergman

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/06 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/49805 ,  H01L23/49838 ,  H01L2224/05005 ,  H01L2224/05012 ,  H01L2224/0612 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2224/45099

Abstract: Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row.

Abstract translation: 公开了没有引线的封装半导体器件的实施例。 一个实施例包括限定边界并具有底表面的半导体芯片和无引线封装结构，并且包括暴露在封装结构的底表面处的三个或更多个焊盘。 每个垫片都位于一个单列排列中。

公开(公告)号：US09196537B2

公开(公告)日：2015-11-24

申请号：US13967164

申请日：2013-08-14

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth Van Gemert ,  Hartmut Buenning ,  Tonny Kamphuis ,  Sascha Moeller ,  Christian Zenz

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/782 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die. Each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance from a vertical edge of the individual device die.

Abstract translation: 与示例性实施例一致，存在用于组装晶片级芯片尺寸处理（WLCSP）晶片的方法; 晶片具有顶侧表面和背面表面，以及在顶侧表面上具有电触头的多个器件裸片。 该方法包括对晶片的背面进行背面研磨至厚度。 在晶片的背面上模制厚度保护层。 将晶片安装在锯片上; 沿着多个器件裸片的锯条，晶片被锯切，锯切发生在第一切口的刀片和背面晶片厚度的深度上。 再次，晶片沿着多个器件裸片的锯条被锯切，锯切发生在第二切口的刀片上，第二切口比第一切口窄，并锯切到保护层厚度的深度。 将多个器件裸片分离为单个器件管芯。 每个单独的器件管芯在背面具有保护层，保护层具有与单独器件管芯的垂直边缘的间隔距离。

公开(公告)号：US20150278673A1

公开(公告)日：2015-10-01

申请号：US14242031

申请日：2014-04-01

Applicant: NXP B.V.

Inventor： Christian Zenz ,  Tonny Kamphuis ,  Johannes Wilhelmus van Rijckevorsel ,  Bodin Kasemset ,  David Ceccarelli ,  Boudewijn van Blokland ,  Patrick Schoengrundner

IPC: G06K19/077

CPC classification number: G06K19/07754 ,  G06K19/07745 ,  G06K19/07769 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/8592 ,  Y10T29/49018 ,  H01L2924/00014

Abstract: Dual-interface Integrated Circuit (IC) card components and methods for manufacturing the dual-interface IC card components are described. In an embodiment, a dual-interface IC card component includes a single-sided contact base structure, which includes a substrate with an electrical contact layer. On the single-sided contact base structure, one or more antenna contact leads are attached to the single-sided contact base structure to form a dual-interface contact structure, which is a component of a dual-interface IC card. Other embodiments are also described.

Abstract translation: 描述了用于制造双接口IC卡组件的双接口集成电路（IC）卡组件和方法。 在一个实施例中，双接口IC卡部件包括单面接触基部结构，其包括具有电接触层的基板。 在单面接触基体结构上，一个或多个天线接触引线附接到单面接触基底结构以形成双界面接触结构，其是双接口IC卡的组件。 还描述了其它实施例。

公开(公告)号：US08679963B2

公开(公告)日：2014-03-25

申请号：US13916430

申请日：2013-06-12

Applicant: NXP B.V.

Inventor： Jan Gulpen ,  Tonny Kamphuis ,  Pieter Hochstenbach ,  Leo Van Gemert ,  Eric Van Grunsven ,  Marc De Samber

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L24/11 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.

Abstract translation: 芯片级封装具有半导体管芯，其具有以每单位面积的焊盘密度排列的管芯接合焊盘的阵列，嵌入在具有支撑导电触头阵列的表面的模制模具支撑体中，每个触点通过电连接 导致相应的一个管芯接合焊盘。

公开(公告)号：US20130264691A1

公开(公告)日：2013-10-10

申请号：US13857091

申请日：2013-04-04

Applicant: NXP B.V.

Inventor： Tonny Kamphuis ,  Leonardus Antonius Elisabeth van Gemert ,  Caroline Catharina Maria Beelen-Hendrikx

IPC: H01L23/552 ,  H01L23/60 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/6835 ,  H01L23/3185 ,  H01L23/544 ,  H01L23/60 ,  H01L24/05 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

公开(公告)号：US09842776B2

公开(公告)日：2017-12-12

申请号：US14994590

申请日：2016-01-13

Applicant: NXP B.V.

Inventor： John Suman Nakka ,  Tonny Kamphuis ,  Roelf Anco Jacob Groenhuis

IPC: H01L21/78 ,  H01L21/02 ,  H01L23/31 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/304 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/11

Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.