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    METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES
    71.
    发明申请
    METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
    制造非易失性存储器件的方法

    公开(公告)号：US20150236111A1

    公开(公告)日：2015-08-20

    申请号：US14683635

    申请日：2015-04-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang-Hyun Lee ,  Byung-Kyu Cho ,  Jang-Hyun You ,  Albert Fayrushin

    IPC: H01L29/423 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L21/02

    CPC classification number: H01L29/42364 ,  H01L21/02109 ,  H01L21/02304 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

    Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.

    Abstract translation: 非易失性存储器件包括栅极结构，绝缘层图案和隔离结构。 在第一方向上彼此间隔开的多个栅极结构形成在基板上。 栅结构的栅极在基本上垂直于第一方向的第二方向上延伸。 衬底包括在第二方向上交替且重复地形成的有源区和场区。 绝缘层图案形成在栅极结构之间并且其中具有第二气隙。 在每个场区域的基板上形成有在第一方向上延伸并且在栅极结构之间具有第一空气间隙，绝缘层图案和隔离结构的隔离结构。

    Crack control for substrate separation
    75.
    发明授权
    Crack control for substrate separation 有权
    基板分离裂纹控制

    公开(公告)号：US08946054B2

    公开(公告)日：2015-02-03

    申请号：US13866669

    申请日：2013-04-19

    Applicant: International Business Machines Corporation

    Inventor： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Kuen-Ting Shiu

    IPC: H01L21/30 ,  H01L21/02 ,  H01L21/306

    CPC classification number: H01L21/7813 ,  H01L21/02109 ,  H01L21/02323 ,  H01L21/306

    Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.

    Abstract translation: 用于分离转移层的方法包括在基板上形成裂纹引导层并在裂纹引导层上形成器件层。 通过将裂纹引导层暴露于减少在与裂纹引导层相邻的界面处的附着力的气体，裂纹引导层被削弱。 在器件层上形成应力诱导层，以帮助通过裂纹引导层和/或界面引发裂纹。 通过传播裂纹将器件层从衬底移除。

    Sputter and surface modification etch processing for metal patterning in integrated circuits
    77.
    发明授权
    Sputter and surface modification etch processing for metal patterning in integrated circuits 有权
    集成电路中金属图案化的溅射和表面改性蚀刻处理

    公开(公告)号：US08633117B1

    公开(公告)日：2014-01-21

    申请号：US13671186

    申请日：2012-11-07

    Applicant: International Business Machines Corporation

    Inventor： Cyril Cabral ,  Benjamin L. Fletcher ,  Nicholas C. M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L23/535 ,  H01L21/02109 ,  H01L21/31111 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines. In another embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, wherein the layer of conductive metal is an intermediate layer in the multi-layer structure, etching the multi-layer structure to expose the conductive metal, sputter etching conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines, forming a liner that surrounds the conductive lines, subsequent to the sputter etching, and depositing a dielectric layer on the multi-layer structure.

    Abstract translation: 在一个实施例中，在集成电路中制造导线包括提供制造在晶片上的多层结构中的导电金属层，并使用甲醇等离子体溅射蚀刻导电金属，其中在溅射之后保留的部分导电金属 蚀刻形成导电线。 在另一个实施例中，在集成电路中制造导线包括提供制造在晶片上的多层结构中的导电金属层，其中导电金属层是多层结构中的中间层， 层结构以暴露导电金属，使用甲醇等离子体溅射蚀刻导电金属，其中在溅射蚀刻之后保留的部分导电金属形成导电线，形成围绕导电线的衬垫，在溅射蚀刻之后，以及 在多层结构上沉积介电层。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    79.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100330812A1

    公开(公告)日：2010-12-30

    申请号：US12819708

    申请日：2010-06-21

    Applicant: Shinichi Akiyama ,  Kazuya Okubo ,  Nobuyuki Ohtsuka

    Inventor： Shinichi Akiyama ,  Kazuya Okubo ,  Nobuyuki Ohtsuka

    IPC: H01L21/31

    CPC classification number: H01L21/02109 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02321 ,  H01L21/823857

    Abstract: A method for manufacturing a semiconductor device includes forming a first-conductivity-type well and a second-conductivity-type well in a silicon substrate; stacking a first high-dielectric-constant insulating film and a first cap dielectric film above the silicon substrate; removing at least the first cap dielectric film from above the second-conductivity-type well; conducting a first annealing at a first temperature to cause an element included in the first cap dielectric film to diffuse into the first high-dielectric-constant insulating film disposed above the first-conductivity-type well; after the first annealing, stacking a second high-dielectric-constant insulating film and a second cap dielectric film above the silicon substrate; removing the second cap dielectric film disposed above the first-conductivity-type well; and conducting a second annealing at a second temperature lower than the first temperature to cause an element included in the second cap dielectric film to diffuse into the second high-dielectric-constant insulating film disposed above the second-conductivity-type well.

    Abstract translation: 一种制造半导体器件的方法包括在硅衬底中形成第一导电型阱和第二导电型阱; 在硅衬底之上堆叠第一高介电常数绝缘膜和第一帽电介质膜; 从所述第二导电型阱的上方至少去除所述第一盖电介质膜; 在第一温度下进行第一退火，使包含在第一盖电介质膜中的元素扩散到位于第一导电型阱之上的第一高介电常数绝缘膜; 在第一退火之后，在硅衬底上层叠第二高介电常数绝缘膜和第二帽电介质膜; 去除设置在第一导电型阱之上的第二盖电介质膜; 以及在比所述第一温度低的第二温度下进行第二退火，以使包含在所述第二盖电介质膜中的元素扩散到位于所述第二导电型阱之上的所述第二高介电常数绝缘膜中。

    Method for coating ultra-thin resist films
    80.
    发明授权
    Method for coating ultra-thin resist films 有权
    超薄抗蚀剂膜的涂布方法

    公开(公告)号：US06326319B1

    公开(公告)日：2001-12-04

    申请号：US09609746

    申请日：2000-07-03

    Applicant: Christopher L. Pike ,  Khanh B. Nguyen ,  Christopher F. Lyons

    Inventor： Christopher L. Pike ,  Khanh B. Nguyen ,  Christopher F. Lyons

    IPC: H01F1002

    CPC classification number: H01L21/02312 ,  G03F7/16 ,  G03F7/162 ,  H01L21/02109 ,  H01L21/02307 ,  H01L21/312 ,  H01L21/3125

    Abstract: There is provided a method for applying a lower viscosity coating liquid onto a semiconductor wafer substrate so as to prevent adhesion loss and to maintain low defect level characteristics. This is achieved by priming the substrate with a bonding agent at a temperature in the range of 18° C. to 50° C. for a short amount of time. This is performed prior to the application of a liquid solvent. As a result, there is overcome the problems of poor adhesion to the substrates and high defect levels in the coated UTR films.

    Abstract translation: 提供了一种将低粘度涂布液施加到半导体晶片衬底上以防止粘附损失并保持低缺陷水平特性的方法。 这是通过用粘合剂在18℃至50℃的温度范围内引发基底短时间来实现的。 这是在施加液体溶剂之前进行的。 结果，克服了在涂覆的UTR膜中对基材的粘附性差和高缺陷水平的问题。

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