公开(公告)号：US20160190027A1

公开(公告)日：2016-06-30

申请号：US15065533

申请日：2016-03-09

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Hamid R. Azimi ,  John S. Guzek

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/50 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/96 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4679 ,  H05K3/4682 ,  H05K2201/09918 ,  H05K2203/1536 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.

Abstract translation: 描述形成模制板无芯封装结构的方法。 这些方法和结构可以包括使用大面板格式制造嵌入式模具封装并使用模制来提高面板的刚度，以及将模具嵌入非牺牲模具材料中。 所描述的方法和结构包括制造具有低翘曲的薄的无芯基板结构的方法。

公开(公告)号：US09257380B2

公开(公告)日：2016-02-09

申请号：US14624873

申请日：2015-02-18

Applicant: Intel Corporation

Inventor： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L21/02 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

公开(公告)号：US20240030147A1

公开(公告)日：2024-01-25

申请号：US17871359

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Gang Duan ,  Hamid R. Azimi ,  Rahul Manepalli ,  Srinivas V. Pietambaram

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/473 ,  H01L25/00 ,  H01L25/10 ,  H01L21/48 ,  H10B80/00 ,  G02B6/12

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L25/0655 ,  H01L23/473 ,  H01L25/50 ,  H01L25/105 ,  H01L21/4857 ,  H01L25/0652 ,  H10B80/00 ,  H01L21/4853 ,  G02B6/12007 ,  H01L24/16

Abstract: Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.

公开(公告)号：US20240030065A1

公开(公告)日：2024-01-25

申请号：US17871443

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Gang Duan ,  Hamid R. Azimi ,  Rahul Manepalli ,  Srinivas V. Pietambaram

IPC: H01L21/768 ,  H05K7/20 ,  H05K1/11 ,  H01L23/528 ,  H01L23/15

CPC classification number: H01L21/76895 ,  H01L21/7685 ,  H01L21/76816 ,  H05K7/20254 ,  H05K7/20409 ,  H05K1/111 ,  H01L23/528 ,  H01L23/15

Abstract: Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.

公开(公告)号：US20150179559A1

公开(公告)日：2015-06-25

申请号：US14624873

申请日：2015-02-18

Applicant: Intel Corporation

Inventor： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  H01L23/482 ,  H01L23/522

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：US08987065B2

公开(公告)日：2015-03-24

申请号：US14090461

申请日：2013-11-26

Applicant: Intel Corporation

Inventor： Ravi K. Nailla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：US20240030204A1

公开(公告)日：2024-01-25

申请号：US17871413

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Gang Duan ,  Hamid R. Azimi ,  Rahul Manepalli ,  Srinivas V. Pietambaram

IPC: H01L25/16 ,  H01L23/427 ,  H01L23/538 ,  G02B6/12

CPC classification number: H01L25/167 ,  H01L23/427 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  G02B6/12004

Abstract: Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.

公开(公告)号：US20230317592A1

公开(公告)日：2023-10-05

申请号：US17711749

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Hamid R. Azimi ,  Sri Chaitra Jyotsna Chavali ,  Tarek A. Ibrahim ,  Wei-Lun K Jen ,  Rahul Manepalli ,  Kevin T. McCarthy

IPC: H01L23/498

CPC classification number: H01L23/49894 ,  H01L23/49822 ,  H01L23/49827

Abstract: In one embodiment, a package substrate includes a substrate core, buildup layers, and one or more conductive traces. The substrate core includes at least one dielectric layer with hollow glass fibers. The buildup layers include dielectric layers below and above the substrate core.

公开(公告)号：US09312233B2

公开(公告)日：2016-04-12

申请号：US13928796

申请日：2013-06-27

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Hamid R. Azimi ,  John S. Guzek

IPC: H05K13/04 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H05K3/00 ,  H05K3/46

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/96 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4679 ,  H05K3/4682 ,  H05K2201/09918 ,  H05K2203/1536 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.

Abstract translation: 描述形成模制板无芯封装结构的方法。 这些方法和结构可以包括使用大面板格式制造嵌入式模具封装并使用模制来提高面板的刚度，以及将模具嵌入非牺牲模具材料中。 所描述的方法和结构包括制造具有低翘曲的薄的无芯基板结构的方法。