公开(公告)号：US12068172B2

公开(公告)日：2024-08-20

申请号：US16525985

申请日：2019-07-30

申请人： Intel Corporation

发明人： Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Wei-Lun K. Jen ,  Steve S. Cho ,  Jason M. Gamba ,  Javier Soto Gonzalez

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L21/4846 ,  H01L21/481 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2924/19041 ,  H01L2924/19105

摘要： Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

公开(公告)号：US11735531B2

公开(公告)日：2023-08-22

申请号：US17374886

申请日：2021-07-13

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta ,  Javier Soto Gonzalez ,  Kwangmo Lim

IPC分类号： H01L23/538 ,  H01L23/00

CPC分类号： H01L23/5389 ,  H01L23/00 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2924/18162

摘要： A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US20180182707A1

公开(公告)日：2018-06-28

申请号：US15389100

申请日：2016-12-22

申请人： Intel Corporation

发明人： Adel A. Elsherbini ,  Henning Braunisch ,  Javier Soto Gonzalez ,  Shawna M. Liff

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0655 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1403 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703

摘要： An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

公开(公告)号：US09691727B2

公开(公告)日：2017-06-27

申请号：US14686210

申请日：2015-04-14

申请人： Intel Corporation

发明人： Javier Soto Gonzalez ,  Charavana K. Gurumurthy ,  Robert M. Nickerson ,  Debendra Mallik

IPC分类号： H05K3/46 ,  H05K3/40 ,  H05K3/34 ,  H05K3/28 ,  H05K3/24 ,  H05K3/20 ,  H05K3/00 ,  H05K1/11 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L24/17 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/2064 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/20 ,  H05K3/244 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05599

摘要： A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

公开(公告)号：US20160284630A1

公开(公告)日：2016-09-29

申请号：US14653033

申请日：2014-07-11

申请人： INTEL CORPORATION

发明人： Alejandro Levander ,  Tatyana Andryushchenko ,  David Staines ,  Mauro Kobrinsky ,  Aleksandar Aleksov ,  Dilan Seneviratne ,  Javier Soto Gonzalez ,  Srinivas Pietambaram ,  Rafiqul Islam

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/4985 ,  B23B5/16 ,  B32B27/08 ,  B32B27/283 ,  B32B2307/54 ,  B32B2307/7265 ,  B32B2439/00 ,  B32B2457/00 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/48227 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0715 ,  H01L2924/15747 ,  H01L2924/15791 ,  H05K1/0283 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.

摘要翻译： 这里通常讨论的是可以包括可拉伸和可弯曲装置的系统和方法。 根据一个实例，一种方法可以包括（1）在面板上沉积第一弹性体材料，（2）在弹性体材料上层叠微量材料，（3）处理微量材料以将痕量材料图案化成一个或多个迹线 或更多的接合垫，（4）将管芯附接到所述一个或多个接合焊盘，或（5）在所述一个或多个迹线上和周围沉积第二弹性体材料，所述接合焊盘和所述管芯以将所述一个或多个 迹线和第一和第二弹性体材料中的一个或多个接合焊盘。

公开(公告)号：US10978399B2

公开(公告)日：2021-04-13

申请号：US16474589

申请日：2017-03-31

申请人： Intel Corporation

发明人： Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Sai Boyapati ,  Wei-Lun Kane Jen ,  Javier Soto Gonzalez

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/13 ,  H01L23/495 ,  H01L23/532

摘要： A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85° and 95°.

公开(公告)号：US10971453B2

公开(公告)日：2021-04-06

申请号：US16335845

申请日：2016-09-30

申请人： Intel Corporation

发明人： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Henning Braunisch ,  Krishna Bharath ,  Javier Soto Gonzalez ,  Javier A. Falcon

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L25/03 ,  H01L23/498 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

摘要： Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US10971416B2

公开(公告)日：2021-04-06

申请号：US16526497

申请日：2019-07-30

申请人： Intel Corporation

发明人： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC分类号： H01L23/52 ,  H01L23/12 ,  H01L23/48 ,  H01L21/48 ,  H01L23/498

摘要： Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US10461032B2

公开(公告)日：2019-10-29

申请号：US13757153

申请日：2013-02-01

申请人： Intel Corporation

发明人： Javier Soto Gonzalez ,  Houssam Jomaa

IPC分类号： H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/14

摘要： A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

公开(公告)号：US20160280535A1

公开(公告)日：2016-09-29

申请号：US14671549

申请日：2015-03-27

申请人： Intel Corporation

发明人： Kyu Oh Lee ,  Zheng Zhou ,  Islam A. Salama ,  Feras Eid ,  Sasha N. Oster ,  Lay Wai Kong ,  Javier Soto Gonzalez

IPC分类号： B81B3/00 ,  B81C1/00

CPC分类号： B81B7/0077 ,  B81C2203/0109

摘要： Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

摘要翻译： 描述形成传感器集成封装器件和由此形成的结构的方法。 一个实施例包括提供衬底芯，其中第一导电迹线结构和第二导电迹线结构设置在衬底芯上，在第一导电迹线结构和第二导电迹线结构之间形成空腔，并将磁体放置在抗蚀剂上 设置在第一和第二导电迹线结构中的每一个的一部分上的材料，其中抗蚀剂材料不在空腔上延伸。