公开(公告)号：US20150003000A1

公开(公告)日：2015-01-01

申请号：US13928796

申请日：2013-06-27

Applicant: Rahul N. MANEPALLI ,  Hamid R. AZIMI ,  John S. GUZEK

Inventor： Rahul N. MANEPALLI ,  Hamid R. AZIMI ,  John S. GUZEK

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/96 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4679 ,  H05K3/4682 ,  H05K2201/09918 ,  H05K2203/1536 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.

Abstract translation: 描述形成模制板无芯封装结构的方法。 这些方法和结构可以包括使用大面板格式制造嵌入式模具封装并使用模制来提高面板的刚度，以及将模具嵌入非牺牲模具材料中。 所描述的方法和结构包括制造具有低翘曲的薄的无芯基板结构的方法。

公开(公告)号：US08618652B2

公开(公告)日：2013-12-31

申请号：US12761782

申请日：2010-04-16

Applicant: Ravi K Nalla ,  John S Guzek ,  Javier Soto Gonzalez ,  Drew W Delaney ,  Hamid R Azimi

Inventor： Ravi K Nalla ,  John S Guzek ,  Javier Soto Gonzalez ,  Drew W Delaney ,  Hamid R Azimi

IPC: H01L23/053

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

公开(公告)号：US20110101516A1

公开(公告)日：2011-05-05

申请号：US12590138

申请日：2009-11-03

Applicant: John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

Inventor： John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

IPC: H01L23/10 ,  H01L21/00 ,  H01L21/66

CPC classification number: H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract translation: 微电子封装包括具有第一表面区域（125）的第一衬底（120）和具有第二表面区域（135）的第二衬底（130）。 第一衬底包括在第一表面处具有第一间距（127）的第一组互连（126）和在第二表面（222）处具有第二间距（129）的第二组互连（128）。 第二衬底使用第二组互连件耦合到第一衬底，并且包括具有第三间距（237）和第三组互连（236）的第三组互连（236），并且内部导电层（233,234）以微孔（ 240）。 第一间距小于第二间距，第二间距小于第三间距，第一表面积小于第二表面积。

公开(公告)号：US08035218B2

公开(公告)日：2011-10-11

申请号：US12590138

申请日：2009-11-03

Applicant: John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

Inventor： John S. Guzek ,  Mahadevan Survakumar ,  Hamid R. Azimi

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

公开(公告)号：US20110318850A1

公开(公告)日：2011-12-29

申请号：US13225745

申请日：2011-09-06

Applicant: John S. Guzek ,  Mahadevan Suryakumar ,  Hamid R. Azimi

Inventor： John S. Guzek ,  Mahadevan Suryakumar ,  Hamid R. Azimi

IPC: H01L21/66

CPC classification number: H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract translation: 微电子封装包括具有第一表面区域（125）的第一衬底（120）和具有第二表面区域（135）的第二衬底（130）。 第一衬底包括在第一表面处具有第一间距（127）的第一组互连（126）和在第二表面（222）处具有第二间距（129）的第二组互连（128）。 第二衬底使用第二组互连件耦合到第一衬底，并且包括具有第三间距（237）和第三组互连（236）的第三组互连（236），并且内部导电层（233,234）以微孔（ 240）。 第一间距小于第二间距，第二间距小于第三间距，第一表面积小于第二表面积。

公开(公告)号：US07330357B2

公开(公告)日：2008-02-12

申请号：US10667694

申请日：2003-09-22

Applicant: Gilroy J. Vandentop ,  Hamid R. Azimi

Inventor： Gilroy J. Vandentop ,  Hamid R. Azimi

IPC: H05K7/10 ,  H05K7/12

CPC classification number: H01L24/10 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/13 ,  H01L2221/68345 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/30105 ,  H05K3/326 ,  H05K3/386 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/09909 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements to be electrically coupled to a second electrical contact of an integrated circuit die.

Abstract translation: 系统可以包括多个柔性导电元件，多个柔性导电元件中的一个导电元件的第一端被电耦合到集成电路基板的第一电接触件和多个柔性导电元件中的一个的第二端 元件被电耦合到集成电路管芯的第二电接触件。

公开(公告)号：US20140084467A1

公开(公告)日：2014-03-27

申请号：US14090461

申请日：2013-11-26

Applicant: Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

Inventor： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。