公开(公告)号：US20140322909A1

公开(公告)日：2014-10-30

申请号：US14323677

申请日：2014-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC: H01L21/768

CPC classification number: H01L24/81 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/811 ,  H01L2224/8136 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Abstract translation: 集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。 金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。 金属线包括双镶嵌结构。 集成电路结构还包括覆盖金属线的凸块。

公开(公告)号：US20140217156A1

公开(公告)日：2014-08-07

申请号：US14250546

申请日：2014-04-11

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Aya MUTO ,  Masayoshi Shinkai

IPC: H01L23/00

CPC classification number: H01L24/27 ,  B23K1/0016 ,  H01L23/49513 ,  H01L23/49541 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16245 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/2747 ,  H01L2224/29019 ,  H01L2224/291 ,  H01L2224/29561 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/32245 ,  H01L2224/33151 ,  H01L2224/33181 ,  H01L2224/811 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83104 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83385 ,  H01L2224/83815 ,  H01L2224/83951 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A joining method that allows joining processing to be carried out simultaneously at a plurality of portions without being influenced by a supply time restriction on a joining material, and a semiconductor device manufacturing method using the joining method are provided. A chip and a lead frame are tentatively assembled having a solid solder block interposed therebetween. The solder block is provided with protruding parts that protrude in one direction. The protruding parts are inserted into solder supply ports of the lead frame, whereby the chip and the lead frame are tentatively assembled. Subsequently, the chip and the lead frame are fed into a reflow oven, and the solder block is melted and thereafter solidified. Thus, the chip and the lead frame are joined to each other.

Abstract translation: 提供一种接合方法，其允许在多个部分同时进行接合处理，而不受对接合材料的供应时间限制的影响，并且提供使用该接合方法的半导体器件制造方法。 暂时组装了芯片和引线框架，其间插入有固体焊料块。 焊块设有沿一个方向突出的突出部分。 突出部分插入引线框架的焊料供给口，由此临时组装芯片和引线框架。 随后，芯片和引线框架被馈送到回流炉中，并且焊料块熔化并随后固化。 因此，芯片和引线框架彼此连接。

公开(公告)号：US08785250B2

公开(公告)日：2014-07-22

申请号：US12112192

申请日：2008-04-30

Applicant: Nirmal Sharma ,  Virgil Ararao

Inventor： Nirmal Sharma ,  Virgil Ararao

IPC: H01L21/00 ,  H01L23/52

CPC classification number: H01L24/81 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/16257 ,  H01L2224/16258 ,  H01L2224/1626 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/811 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92143 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.

Abstract translation: 半导体封装的制造包括将导电材料放置在来自引线框架的突起上以形成第一组件，在突起周围形成非导电掩模，以及将模具放置在第一组件上，所述管芯具有有效区域。 制造还可以包括回流导电材料以形成第二组件，使得连接从模具有源区域通过导电材料延伸到突出部。 半导体封装包括具有突起的引线框架，回流到突起的导电材料和具有通过回流焊料耦合到突起的有源区域的管芯。

公开(公告)号：US08497148B2

公开(公告)日：2013-07-30

申请号：US13189057

申请日：2011-07-22

Applicant: Bruce C. S. Chou

Inventor： Bruce C. S. Chou

IPC: H01L21/58 ,  H01L23/48

CPC classification number: B81B3/0018 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0109 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13009 ,  H01L2224/13138 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/8009 ,  H01L2224/80092 ,  H01L2224/80931 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L21/76898 ,  H01L2924/01014 ,  H01L2924/00

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract translation: 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。

公开(公告)号：US08237271B2

公开(公告)日：2012-08-07

申请号：US11765055

申请日：2007-06-19

Applicant: Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

Inventor： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

IPC: H01L23/48

CPC classification number: H01L21/6835 ,  H01L24/11 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06183 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16137 ,  H01L2224/16238 ,  H01L2224/17183 ,  H01L2224/81005 ,  H01L2224/811 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01054 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83851 ,  H01L2224/81

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract translation: 本发明允许使用尽可能短的信号路径进行直接芯片到芯片的连接。

公开(公告)号：US20120187577A1

公开(公告)日：2012-07-26

申请号：US13439198

申请日：2012-04-04

Applicant: Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

Inventor： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L24/11 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06183 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16137 ,  H01L2224/16238 ,  H01L2224/17183 ,  H01L2224/81005 ,  H01L2224/811 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01054 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83851 ,  H01L2224/81

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract translation: 本发明允许使用尽可能短的信号路径进行直接芯片到芯片的连接。

公开(公告)号：US20100187684A1

公开(公告)日：2010-07-29

申请号：US12616920

申请日：2009-11-12

Applicant: Kai-Ming Ching

Inventor： Kai-Ming Ching

IPC: H01L23/498 ,  H01L21/50 ,  H01L21/60

CPC classification number: H01L24/05 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02126 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16059 ,  H01L2224/16147 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.

Abstract translation: 堆叠和对准多个集成电路的方法和系统。 该方法包括以下步骤：提供具有至少一个漏斗形插座的第一集成电路，提供第二集成电路，将第二集成电路上的至少一个突起与至少一个漏斗形插座对准，并将第一集成电路 集成电路到第二集成电路。 该系统包括具有至少一个漏斗形插座，设置在漏斗形插座内部的金属化扩散屏障和第二集成电路的第一集成电路。 所述至少一个漏斗形插座适于接收第二集成电路的一部分。

公开(公告)号：US07726543B2

公开(公告)日：2010-06-01

申请号：US12036449

申请日：2008-02-25

Applicant: Ghassem Azdasht

Inventor： Ghassem Azdasht

IPC: B23K31/02

CPC classification number: H01L24/81 ,  B23K1/0056 ,  B23K3/0607 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/4853 ,  H01L2224/75611 ,  H01L2224/811 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3447 ,  H05K3/3478 ,  H05K2203/0195 ,  H05K2203/041 ,  H05K2203/111 ,  H01L2924/00

Abstract: A method for the production of a soldered joint between at least two contact partners (22, 23) of a bonding arrangement (21), with a formed piece of solder material (27) being arranged at a distance to the bonding arrangement. The formed piece of solder material is at least partially melted off. The at least partially melted off formed piece of solder material being thrust against a bonding arrangement in such a way that both bonding partners are wetted in a bonding area to establish an electrically conductive bonding.

Abstract translation: 一种用于在焊接装置（21）的至少两个接触对接体（22,23）之间生产焊接接头的方法，其中形成的焊料材料（27）布置成与接合装置一段距离。 成形的焊料材料至少部分熔化掉。 至少部分熔化的成形的焊料材料片以这样一种方式推压接合装置，使得两个粘合伙伴在接合区域中被润湿以建立导电接合。

公开(公告)号：US20090051046A1

公开(公告)日：2009-02-26

申请号：US12222555

申请日：2008-08-12

Applicant: Shunpei Yamazaki ,  Mikio Yukawa

Inventor： Shunpei Yamazaki ,  Mikio Yukawa

IPC: H01L21/50 ,  H01L23/48

CPC classification number: H01L23/528 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/08146 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/80895 ,  H01L2224/81001 ,  H01L2224/811 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83138 ,  H01L2224/83851 ,  H01L2224/83907 ,  H01L2224/90 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor substrate provided with an integrated circuit is polished by CMP or the like, and the semiconductor substrate is made into a thin film by forming an embrittlement layer in the semiconductor substrate and separating a part of the semiconductor substrate; thus, semiconductor chips such as IC chips and LSI chips which are thinner than ever are obtained. Moreover, such thinned LSI chips are stacked and electrically connected through wirings penetrating through the semiconductor substrate; thus, a three dimensional semiconductor integrated circuit with improved packing density is obtained.

Abstract translation: 通过CMP等对具有集成电路的半导体基板进行研磨，通过在半导体基板上形成脆化层并分离半导体基板的一部分，将半导体基板制成薄膜; 因此，获得比以往更薄的诸如IC芯片和LSI芯片的半导体芯片。 此外，这种稀薄的LSI芯片通过穿过半导体衬底的布线堆叠并电连接; 从而获得具有改进的堆积密度的三维半导体集成电路。

公开(公告)号：US20080230879A1

公开(公告)日：2008-09-25

申请号：US12112192

申请日：2008-04-30

Applicant: Nirmal Sharma ,  Virgil Ararao

Inventor： Nirmal Sharma ,  Virgil Ararao

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L24/81 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/16257 ,  H01L2224/16258 ,  H01L2224/1626 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/811 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92143 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.

Abstract translation: 半导体封装的制造包括将导电材料放置在来自引线框架的突起上以形成第一组件，在突起周围形成非导电掩模，以及将模具放置在第一组件上，所述管芯具有有效区域。 制造还可以包括回流导电材料以形成第二组件，使得连接从模具有源区域通过导电材料延伸到突出部。 半导体封装包括具有突起的引线框架，回流到突起的导电材料和具有通过回流焊料耦合到突起的有源区域的管芯。